MC68HC908JK1 Datasheet, PDF (132/210 Pages) Motorola, Inc – MC68HC908JK1

Timer Interface Module (TIM)
Technical Data
132
Address: $0025
Bit 7
Read: CH0F
Write: 0
Reset: 0
TSC0
6
CH0IE
0
5
MS0B
0
4
MS0A
0
3
2
ELS0B ELS0A
0
0
1
Bit 0
TOV0 CH0MAX
0
0
Address: $0028 TSC1
Bit 7
6
5
4
3
2
1
Bit 0
Read: CH1F
0
CH1IE
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-7. TIM Channel Status and Control Registers (TSC0:TSC1)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE=1), clear
CHxF by reading the TIM channel x status and control register with
CHxF set and then writing a logic zero to CHxF. If another interrupt
request occurs before the clearing sequence is complete, then writing
logic zero to CHxF has no effect. Therefore, an interrupt request
cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic one to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on
channel x. Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
Timer Interface Module (TIM)
MC68H(R)C908JL3 — Rev. 1.0
MOTOROLA