MC68HC908JK1 Datasheet, PDF (105/210 Pages) Motorola, Inc – MC68HC908JK1

Monitor ROM (MON)
Functional Description
If V_DD +V_HI is applied to IRQ1 and PTB3 is low upon monitor mode
entry (Table 9-1 condition set 1), the bus frequency is a divide-by-two of
the external clock input to OSC1. If PTB3 is high with V_DD +V_HI applied
to IRQ1 upon monitor mode entry (Table 9-1 condition set 2), the bus
frequency is a divide-by-four of the external clock input to OSC1. Holding
the PTB3 pin low when entering monitor mode causes a bypass of a
divide-by-two stage at the oscillator only if V_DD +V_HI is applied to IRQ1.
In this event, the OSCOUT frequency is equal to the 2OSCOUT
frequency, and OSC1 input directly generates internal bus clocks. In this
case, the OSC1 signal must have a 50% duty cycle at maximum bus
frequency.
Entering monitor mode with V_DD + V_HI on IRQ1, the COP is disabled as
long as V_DD + V_HI is applied to either the IRQ1 or the RST. (See Section
7. System Integration Module (SIM) for more information on modes of
operation.)
If entering monitor mode without high voltage on IRQ1 and reset vector
being blank ($FFFE and $FFFF) (Table 9-1 condition set 3, where
applied voltage is V_DD), then all port B pin requirements and conditions,
including the PTB3 frequency divisor selection, are not in effect. This is
to reduce circuit requirements when performing in-circuit programming.
Entering monitor mode with the reset vector being blank, the COP is
always disabled regardless of the state of IRQ1 or the RST.
Figure 9-2. shows a simplified diagram of the monitor mode entry when
the reset vector is blank and IRQ1 = V_DD. An oscillator frequency
(XTALCLK or RCCCLK) of 9.8304MHz is required for a baud rate of
9600.
MC68H(R)C908JL3 — Rev. 1.0
MOTOROLA
Monitor ROM (MON)
Technical Data
105