MC68HC908JK1 Datasheet, PDF (177/210 Pages) Motorola, Inc – MC68HC908JK1

Computer Operating Properly (COP)
COP Control Register
15.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Low byte of reset vector
Write:
Clear COP counter
Reset:
Unaffected by reset
Figure 15-3. COP Control Register (COPCTL)
15.6 Interrupts
The COP does not generate CPU interrupt requests.
15.7 Monitor Mode
The COP is disabled in monitor mode when V_DD + V_HI is present on the
IRQ1 pin or on the RST pin.
15.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power
consumption standby modes.
15.8.1 Wait Mode
The COP continues to operate during wait mode. To prevent a COP
reset during wait mode, periodically clear the COP counter in a CPU
interrupt routine.
MC68H(R)C908JL3 — Rev. 1.0
MOTOROLA
Computer Operating Properly (COP)
Technical Data
177