MC68HC908JK1 Datasheet, PDF (134/210 Pages) Motorola, Inc – MC68HC908JK1

Timer Interface Module (TIM)
Table 10-3. Mode, Edge, and Level Selection
MSxB
X
X
0
0
0
0
0
0
1
1
1
MSxA
0
1
0
0
0
1
1
1
X
X
X
ELSxB
0
0
0
1
1
0
1
1
0
1
1
ELSxA Mode
Configuration
0
Output
Pin under Port Control;
Initial Output Level High
0
Preset
Pin under Port Control;
Initial Output Level Low
1
Capture on Rising Edge Only
0
Input
Capture
Capture on Falling Edge Only
1
Capture on Rising or Falling Edge
1
Toggle Output on Compare
Output
0
Compare Clear Output on Compare
1
or PWM _{Set Output on Compare}
1
Buffered Toggle Output on Compare
0
Output
Compare or
Clear Output on Compare
1
Buffered
PWM
Set Output on Compare
NOTE: Before enabling a TIM channel register for input capture operation, make
sure that the TCHx pin is stable for at least two bus clocks.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIM counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE: When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic zero, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 10-8 shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100% duty cycle level until
the cycle after CHxMAX is cleared.
Technical Data
134
Timer Interface Module (TIM)
MC68H(R)C908JL3 — Rev. 1.0
MOTOROLA