MC68HC908JK1 Datasheet, PDF (104/210 Pages) Motorola, Inc – MC68HC908JK1

Monitor ROM (MON)
9.4.1 Entering Monitor Mode
Table 9-1 shows the pin conditions for entering monitor mode. As
specified in the table, monitor mode may be entered after a POR and will
allow communication at 9600 baud provided one of the following sets of
conditions is met:
1. If IRQ1 = V_DD + V_HI:
– External clock on OSC1 is 4.9125MHz
– PTB3 = low
2. If IRQ1 = V_DD + V_HI:
– External clock on OSC1 is 9.8304MHz
– PTB3 = high
3. If $FFFE & $FFFF is blank (contains $FF):
– The oscillator clock is 9.8304MHz (X-tal or RC)
– IRQ1 = V_DD
Table 9-1. Monitor Mode Entry Requirements and Options
Clock Source
and
Frequency
Bus
Frequency
Comments
V_DD + V_HI
X
0011
OSC1 at
4.9152 MHz
V_DD + V_HI
X
1011
OSC1 at
9.8304 MHz
2.4576 MHz
2.4576 MHz
Bypasses X-tal or RC
oscillator; external clock
driven directly into OSC1.
9600 baud communication
on PTB0. COP disabled.
BLANK
X-tal or RC
V_DD
(contain X X X 1
oscillator at
$FF)
9.8304 MHz
2.4576 MHz
Low-voltage entry to
monitor mode.
9600 baud communication
on PTB0. COP disabled.
V_DD
NOT
BLANK
X-tal or RC
XXXX
oscillator at
desired frequency
XTALCLK ÷ 4
or
RCCLK ÷ 4
Enters User mode.
If $FFFE and $FFFF is
blank, MCU will encounter
an illegal address reset.
Notes:
1. PTB3 = 0: Bypasses the divide-by-two prescaler to SIM when using V_DD + V_HI for monitor mode entry.
The OSC1 clock must be 50% duty cycle for this condition.
2. XTALCLK is the X-tal oscillator output, for MC68HC908xxx. See Figure 8-1.
4. RCCLK is the RC oscillator output, for MC68HRC908xxx. See Figure 8-2.
5. See Table 18-4 for V_DD + V_HI voltage level requirements.
Technical Data
104
Monitor ROM (MON)
MC68H(R)C908JL3 — Rev. 1.0
MOTOROLA