MC68HC908JK1 Datasheet, PDF (147/210 Pages) Motorola, Inc – MC68HC908JK1

Technical Data — MC68H(R)C908JL3
Section 12. I/O Ports
12.1 Contents
12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.4 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . 149
12.4.1 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . 150
12.4.2 Port A Input Pull-up Enable Register (PTAPUE) . . . . . . . . 151
12.5 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.5.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . 153
12.5.2 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . 153
12.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.6.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . 155
12.6.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . 156
12.6.3 Port D Control Register (PDCR). . . . . . . . . . . . . . . . . . . . . 157
12.2 Introduction
Twenty three bidirectional input-output (I/O) pins form three parallel
ports. All I/O pins are programmable as inputs or outputs.
NOTE:
Connect any unused I/O pins to an appropriate logic level, either V_DD or
V_SS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
MC68H(R)C908JL3 — Rev. 1.0
MOTOROLA
I/O Ports
Technical Data
147