MC68HC908JK1 Datasheet, PDF (180/210 Pages) Motorola, Inc – MC68HC908JK1

Low Voltage Inhibit (LVI)
16.4 Functional Description
Figure 16-1 shows the structure of the LVI module. The LVI is enabled
after a reset. The LVI module contains a bandgap reference circuit and
comparator. Setting LVI disable bit (LVID) disables the LVI to monitor
V_DD voltage. The LVI trip voltage selection bits (LVIT1, LVIT0)
determines at which V_DD level the LVI module should take actions.
The LVI module generates one output signal:
LVI Reset — an reset signal will be generated to reset the CPU when
V_DD drops to below the set trip point.
V_DD
LVID
LOW V_DD
DETECTOR
V_DD > LVI_TRIP = 0
V_DD < LVI_TRIP = 1
LVI RESET
LVT1
LVT0
Figure 16-1. LVI Module Block Diagram
16.5 LVI Control Register (CONFIG2/CONFIG1)
Address: $001E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IRQPUD R
R
LVIT1 LVIT0
R
R
R
Write:
Reset: 0
0
0
Not affected Not affected
0
0
0
POR: 0
0
0
0
0
0
0
0
R = Reserved
Figure 16-2. Configuration Register 2 (CONFIG2)
Technical Data
180
Low Voltage Inhibit (LVI)
MC68H(R)C908JL3 — Rev. 1.0
MOTOROLA