MC68HC908JK1 Datasheet, PDF (156/210 Pages) Motorola, Inc – MC68HC908JK1

I/O Ports
12.6.2 Data Direction Register D (DDRD)
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic one to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic zero disables the output buffer.
Address: $0007
Bit 7
6
5
4
3
2
1
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1
Write:
Reset: 0
0
0
0
0
0
0
Figure 12-10. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1. Figure 12-11 shows
the port D I/O logic.
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
DDRDx
PTDx
PTDPU[6:7]
5k
PTDx
READ PTD ($0003)
Technical Data
156
PTD[0:3] To Analog-To-Digital Converter
PTD[4:5] To Timer
Figure 12-11. Port D I/O Circuit
I/O Ports
MC68H(R)C908JL3 — Rev. 1.0
MOTOROLA