MC68HC908JK1 Datasheet, PDF (34/210 Pages) Motorola, Inc – MC68HC908JK1

Memory
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: IF14
0
0
0
0
0
0
0
$FE05
Interrupt Status Register 2
(INT2)
Write:
R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
Read: 0
0
0
0
0
0
0
IF15
$FE06
Interrupt Status Register 3
(INT3)
Write:
R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
$FE07
Read:
R
R
R
R
R
R
R
R
Reserved Write:
$FE08
$FE09
$FE0A
↓
$FE0B
Read:
FLASH Control Register
(FLCR)
Write:
Reset:
Read:
FLASH Block Protect
Register (FLBPR)
Write:
Reset:
Read:
Reserved Write:
0
0
BPR7
0
R
0
0
BPR6
0
R
0
0
BPR5
0
R
0
0
BPR4
0
R
HVEN MASS ERASE PGM
0
0
0
0
0
BPR3 BPR2 BPR1
0
0
0
0
R
R
R
R
Break Address High ^Read: _Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
$FE0C
Register Write:
(BRKH) _{Reset: 0}
0
0
0
0
0
0
0
$FE0D
Break Address low ^Read: _Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Register Write:
(BRKL) _{Reset: 0}
0
0
0
0
0
0
0
Break Status and Control ^Read: _{BRKE BRKA}
0
0
0
0
0
0
$FE0E
Register Write:
(BRKSCR) _{Reset: 0}
0
0
0
0
0
0
0
$FFFF
Read:
COP Control Register
(COPCTL)
Write:
Reset:
Low byte of reset vector
Writing clears COP counter (any value)
Unaffected by reset
= Unimplemented
R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 5)
Technical Data
34
Memory
MC68H(R)C908JL3 — Rev. 1.0
MOTOROLA