M37733MHBXXXFP Datasheet, PDF (9/89 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7. Overflow flag (V)
The overflow flag is effective only when addition or subtraction is
performed with treating a word as a signed binary number. When the
data length flag (m) is “0”, the overflow flag is set if the result of
addition or subtraction is outside the range between – 32768 and
+32767. When the data length flag (m) is “1”, the overflow flag is set
if the result of addition or subtraction is outside the range between
–128 and +127. It is reset in the other cases. The overflow flag can
also be set or reset directly with the SEP or CLV, CLP instructions.
8. Negative flag (N)
The negative flag is set when the result of arithmetic operation or
data transfer is negative (If data length flag (m) is “0”, data bit 15 is
“1”. If data length flag (m) is “1”, data bit 7 is “1”.) It is reset in the
other cases. It can also be set or reset with the SEP or CLP
instructions.
9. Processor interrupt priority level (IPL)
The processor interrupt priority level (IPL) consists of 3 bits and
determines the processor interrupt priority level (0 to 7). Interrupt is
enabled when the interrupt priority level of the device requesting
interrupt (the priority can be set using the interrupt control register) is
higher than the processor interrupt priority level. When interrupt is
enabled, the current processor interrupt priority level is saved in a
stack and the processor interrupt priority level is replaced by the
interrupt priority level of the device requesting the interrupt. Refer to
the section on interrupts for more details.
BUS INTERFACE UNIT
The CPU operates on an internal clock ’s frequency. Internal clock
’s frequency is twice the bus cycle frequency. In order to speed up
processing, a bus interface unit is used to pre-fetch instructions when
the data bus is idle. The bus interface unit synchronizes the CPU
and the bus and pre-fetches instructions. Figure 4 shows the
relationship between the CPU and the bus interface unit. The bus
interface unit has a program address register, a 3-byte instruction
queue buffer, a data address register, and a 2-byte data buffer.
The bus interface unit obtains an instruction code from the memory
and stores it in the instruction queue buffer, obtains data from the
memory and stores it in the data buffer, or writes the data from the
data buffer to the memory.
CPU
D'15 – D'8
D'7 – D'0
A'23 – A'0
Control signal
D15 – D8
D7 – D0
A23 – A0
Bus interface
unit
BHE
R/W
E
ALE
BYTE
HOLD
Fig. 4 Relationship between the CPU and the bus interface unit
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