M37733MHBXXXFP Datasheet, PDF (37/89 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7 6 54 3 210
Address
0 ! ! ! 0 0 0 1 ^{UART0 transmit/receive 3016}
mode register
001 : Clock synchronous
0 : Internal clock
!!! : Not used
0 : always “0”
76 54 3 210
Address
TPM CPL TxS ₁
! CS1 CS2 ^{UART0 transmit/receive 3416}
control register 0
Clock source selection bits
0 0 : Select f2
0 1 : Select f16
1 0 : Select f64
1 1 : Select f512
! : Not used
1 : Disable CTS and RTS
(I/O port)
Data output selection bit
0 : CMOS output
1 : N-channel open-drain output
CLK polarity selection bit
0 : In transmitting, transmit data
is output at the CLK's falling
edge. Not in transmitting,
CLK0 level is “H”.
1 : In transmitting, transmit data
is output at the CLK0's rising
edge. Not in transmitting,
CLK0 level is “L”.
Transfer format selection bit
0 : LSB first
1 : MSB first
7 65 43 2 10
Address
0
TE
UART0 transmit/receive
control register 1
3516
Trasmit enable flag
0 : Receiving is disabled
Fig. 45 Bit configuration of UART0 transmit/receive mode register
and UART0 transmit/receive control register 0/1 in the
transmission clock output multiple-selection mode
Receive
Receive starts when the bit 2 (REk flag) of the UARTk transmit/receive
control register 1 is set to “1”.
The RTSk output level is “H” when the REk flag is “0”, but it is “L” when
the REk flag is “1” and the TIk flag is “0”. Furthermore, the RTSk output
level is “H” again when receiving restarts. The TIk flag is cleared to
“0” by writing dummy data into the transmission buffer register. When
the RTSk output level is “L”, receiving for the receive register is enabled.
UART2 does not have the RTS output function.
When bit 6 (CPL) of the UARTk transmit/receive control register 0 is
“0”, the contents of the receive register is shifted by 1 bit each time
when the receive clock (CLKk) changes from “L” to “H”. When CPL is
“1”, the contents is shifted by 1 bit each time when CLKk changes
from “H” to “L”. These shifts are performed simultaneously with the
data reception from the RXDk pin. When an 8-bit data is received, the
contents of the receive register is transferred to the receive buffer
register and the bit 3 (RIk flag) of the UARTk transmit/receive control
register 1 is set to “1”. In other words, the setting of the RIk flag to “1”
indicates that the receive buffer register contains the received data.
When the TIk flag goes “0”, RTSk output level goes “L” to indicate that
the next data can be received. When the RIk flag changes from “0” to
“1”, the interrupt request bit of the UARTk receive (transmit/receive in
UART2) interrupt control register is set to “1”. Bit 4 (OERk flag) of the
UARTk transmit/receive control register is set to “1” when the next
data is transferred from the receive register to the receive buffer
register while RIk flag is “1”, and the OERk flag indicates that the next
data was transferred to the receive buffer register before the contents
of the receive buffer register was read.
The RIk flag is cleared to “0” when reading the low-order byte to the
receive buffer, when writing “0” to the REk flag, or when setting to be
a parallel port. The OERk flag is cleared to “0” when writing “0” to the
REk flag or when setting to be a parallel port. The FERk, PERk, and
SUMk flags are ineffective in the clock synchronous communication.
The received data in the receive buffer register is read into the data
bus according to the LSB first (beginning at the least significant bit)
when bit 7 (TEM) of the UARTk transmit/receive control register 0 is
“0” or according to the MSB first (beginning at the most significant
bit) when bit 7 is “1”.
As shown in Figure 36, with clock synchronous serial communication,
data cannot be received unless the transmitter is operating because
the receive clock is created from the transmission clock. Therefore,
the transmitter must be operating even when there is no data to be
sent from UARTk to UARTj.
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