M37733MHBXXXFP Datasheet, PDF (52/89 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Single-chip mode [00]
Single-chip mode is entered by connecting the CNVss pin to Vss and
starting from reset. Ports P0 to P4 all function as normal I/O ports.
Port P42 can output clock φ 1 by setting bit 7 of the processor mode
register 0 to “1”. For clock φ 1, refer to Figure 65.
In this mode, signal E is output from pin E. Signal E output, however,
can be stopped by setting the signal output disable selection bit (bit 6
of the oscillation circuit control register 0) to “1”, and it is possible to
switch the E pin function to “L” output. Table 7 shows the function of
the signal output disable selection bit.
(2) Memory expansion mode [01]
Memory expansion mode is entered by setting the processor mode
bits to “01” after connecting the CNVss pin to Vss and starting from
reset.
Pin E becomes the output pin for signal E.
E is an enable signal and is “L” during the data/instruction code read
or data write term. When the internal memory area is read or written,
E can be fixed to “H” by setting the signal output disabe selection bit
(bit 6 of the oscillation circuit control register 0) to “1”.
Port P0 becomes an address output pin and loses its I/O port function.
Port P1 has two functions depending on the level of the BYTE pin. In
both cases, the I/O port function is lost.
When the BYTE pin level is “L”, port P1 functions as an address
output pin while E is “H” and as an odd address data I/O pin while E
is “L”. However, if an internal memory is read, external data is ignored
while E is “L”.
When the BYTE pin level “H”, port P1 functions as an address output
pin.
Port P2 has two functions depending on the level of the BYTE pin. In
both cases, the I/O port function is lost.
When the BYTE pin level is “L”, port P2 functions as an address
output pin while E is “H” and as an even address data I/O pin while E
is “L”. However, if an internal memory is read, external data is ignored
while E is “L”.
When the BYTE pin level is “H”, port P2 functions as an address
output pin while E is “H” and as an even and odd address data I/O pin
while E is “L”. However, if an internal memory is read, external data is
ignored while E is “L”.
Ports P30, P31, P32, and P33 become R/W, BHE, ALE, and HLDA
output pin respectively and lose their I/O port functions.
R/W is a read/write signal which indicates a read when it is “H” and a
write when it is “L”.
BHE is a byte high enable signal which indicates that an odd address
is accessed when it is “L”.
Therefore, two bytes at even and odd addresses are accessed
simultaneously when address A0 is “L” and BHE is “L”.
ALE is an address latch enable signal used to latch the address signal
from a multiplexed signal of address and data. The latch is transparent
while ALE is “H” to let the address signal pass through and held
while ALE is “L”.
HLDA is a hold acknowledge signal and is used to notify externally
when the microcomputer receives HOLD input and enters hold state.
Ports P40 and P41 become HOLD and RDY input pin, respectively,
and lose their output pin function.
HOLD is a hold request signal. It is an input signal used to put the
microcomputer in hold state. HOLD input is accepted when the internal
clock φ falls from “H” level to “L” level while the bus is not used. Ports
P0, P1, P2, P30 and P31 are floating while the microcomputer stays
in hold state. These ports become floating after one cycle of internal
clock φ later than HLDA signal changes to “L” level. At releasing hold
state, these ports are released from floating state after one cycle of
internal clock φ later than HLDA signal changes to “H” level.
RDY is a ready signal. When this signal goes “L”, the internal clock φ
stops at “L”. RDY is used when a slow external memory is attached.
Port P42 becomes a normal I/O port when bit 7 of the processor
mode register 0 is “0” and becomes an output pin for clock φ 1 when
bit 7 is “1”. The φ 1 output is independent of RDY and does not stop
even when internal clock φ stops because of “L” input to the RDY pin.
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