M37733MHBXXXFP Datasheet, PDF (39/89 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bit 6 is the parity enable bit which indicates whether to add parity bit
or not.
Bits 4 to 6 should be set or reset according to the data format of the
communicating devices.
Bit 7 is the sleep selection bit (refer to the next page).
Bit 2 of the UARTi transmit/receive control register 0 is used to
determine whether to use CTSi input or RTSi output. CTSi input is used
if bit 2 is “0” and RTSi output is used if bit 2 is “1”.
If CTSi input is selected, the user can control whether to stop or start
transmission with external CTSi input.
Whether to use CTS and RTS signals is determined by bit 4 of the
UART transmit/receive control register 0. Set bit 4 to “0” when CTS
and RTS signals are used, and to “1” when they are not used.
UART2 has the CTS input function, but that does not have the RTS
output function (refer to Figure 40.)
When CTS and RTS signals are not used, the CTS/RTS pin can be
used as a normal port. The following describes the case when the
CTS and RTS signals are used. If CTS and RTS signals are not used,
the CTSi input condition is unnecessary and there is no RTSi output.
In addition, output driver format of the transmission data output pin
(TXDj), which is CMOS output or N-channel open-drain output, is
selected with bit 5 (TXS) of the UARTj transmit/receive control register
0. CMOS output format is selected when bit 5 is “0”, and N-channel
open-drain output format is selected when bit 5 is “1”. When N-channel
open-drain output format is selected, make sure to pull-up the data
line using a pull-up resistor.
However, UART2 does not have bit 5 (TxS) and the format is always
CMOS output.
In asynchronous serial communication, bits 6 and 7 of the UARTj
transmit/receive control register 0 must be “0”.
Transmission
Transmission is started when the bit 0 (TEi flag) of UARTi transmit/
receive control register 1 is “1”, the bit 1 (TIi flag) is “0”, and CTSi input
is “L” if CTSi input is selected. As shown in Figures 46 and 47, data is
output from the TXDi pin with the start bit and the stop bit or parity bit
specified by the bits 4 to 6 of UARTi transmit/receive mode register.
The data is output beginning at the least significant bit.
The TIi flag indicates whether the transmission butter is empty or not.
It is cleared to “0” when data is written in the transmission buffer and
set to “1” when the contents of the transmission buffer register is
transferred to the transmission register.
When the transmission register becomes empty after the contents
has been transmitted, data is transferred automatically from the
transmission buffer register to the transmission register if the next
transmission start condition is satisfied.
Once transmission has started, the TEi flag, TIi flag, and CTSi signal
(if CTSi input is selected) are ignored until data transmission is
completed.
Therefore, transmission does not stop until it completes even if the
TEi flag is cleared during transmission.
As shown in Figure 46, CTSi input and flags TEi and TIi, which indicate
the transmission start condition, are checked while the TENDi signal
is “H”. Therefore, data can be transmitted continuously if the next
transmission data is written in the transmission buffer register and TIi
flag is cleared to 0 before the TENDi signal goes “H”.
The bit 3 (TXEPTYi flag) of the UARTi transmit/receive control register
0 changes to “1” at the next cycle after the TENDi signal goes “H” and
changes to “0” when transmission starts. Therefore, this flag can be
used to determine whether data transmission is completed.
When the TIi flag changes from “0” to “1”, the interrupt request bit of
the UARTi transmission (transmit/receive in UART2) interrupt control
register is set to “1”.
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