M37733MHBXXXFP Datasheet, PDF (38/89 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ASYNCHRONOUS SERIAL COMMUNICATION
(UART)
Asynchronous serial communication can be performed using 7-, 8-,
or 9-bit length data. The operation is the same for all data lengths.
The following is the description for 8-bit asynchronous communication.
With 8-bit asynchronous communication, the bits 2 to 0 of the UARTi
transmit/receive mode register must be “101”.
Bit 3 is used to select an internal clock or an external clock. If bit 3 is
“0”, an internal clock is selected and if bit 3 is “1”, then external clock
is selected. If an internal clock is selected, the bit 0 (CS0) and bit 1
(CS1) of UARTi transmit/receive control register 0 are used to select
the clock source. When an internal clock is selected for asynchronous
serial communication, the CLKi pin can be used as a normal port.
If the content of the bit rate generator is n, the selected internal or
external clock is divided by (n + 1), then by 16, and passed through a
control circuit to create the UART transmission clock or the UART
receive clock.
If the selected clock is an internal clock fi or an external clock fEXT,
Bit Rate = (fi or fEXT) / {(n + 1) ! 16}
Bit 4 selects 1 stop bit or 2 stop bits.
The bit 5 is a selection bit of odd parity or even parity.
In the odd parity mode, the parity bit is adjusted so that the sum of
the 1’s in the data and parity bit is always odd.
In the even parity mode, the parity bit is adjusted so that the sum of
the 1’s in the data and parity bit is always even.
Transmission clock
(1 / f1 , or 1 / fEXT) ! (n + 1) ! 16
TEi
TIi
CTSi
Write in transmission buffer register
Transmission register ← _Transmission
buffer register
TEN D i
TXDi
TXEPTYi
Start bit
Parity bit Stop bit
ST _{D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP}
Stopped because TEi = “0”
ST _{D0 D1}
Fig. 46 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit is selected
Transmission clock
(1 / f1 , or 1 / fEXT) ! (n + 1) ! 16
TEi
TIi
TEN D i
TXDi
Write in transmission buffer register
Transmission register ← Transmission
buffer register
Start bit
Stop Bit Stop Bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 _{SP SP ST D0 D1 D2 D3 D4 D5} D6 D7 D8 _SP SP
Stopped because
TEi = “0”
ST _{D0 D1 D2}
TXEPTYi
Fig. 47 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits is selected
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