M37733MHBXXXFP Datasheet, PDF (26/89 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TIMER B
Figure 29 shows a block diagram of timer B.
Timer B has three modes; timer mode, event counter mode, and
pulse period measurement/pulse width measurement mode. The
mode is selected with bits 0 and 1 of the timer Bi mode register (i = 0
to 2). Timer B2 can also be used as the clock timer of which clock
source is the main clock or the sub-clock divided by 32. Additionally,
timer B2 can be internally connected to timer B1 (cascade connection).
Each of these modes is described below.
(1) Timer mode [00]
Figure 30 shows the bit configuration of the timer Bi mode register
during the timer mode. Bits 0 and 1 of the timer Bi mode register
must always be “0” in the timer mode.
Bits 6 and 7 are used to select the clock source. The counting of the
selected clock starts when the count start flag is “1” and stops when
it is “0”.
As shown in Figure 15, the timer Bi count start flag is at the same
address as the timer Ai count start flag. The count is decremented.
When the contents of the counter becomes 000016, an interrupt
request occurs and the interrupt request bit of the timer Bi interrupt
control register is set. At the same time, the contents of the reload
register is stored in the counter, and count is continued.
Timer Bi does not have a pulse output function or a gate function like
timer A.
When data is written to timer Bi halted, it is written to the reload register
and the counter. When data is written to timer Bi which is busy, the
data is written to the reload register, but not to the counter. The counter
is reloaded with new data from the reload register at the next reload
time and continues counting. The contents of the counter can be
read at any time.
Data bus (odd)
Clock source selection
f2
f16
f64
f512
• Timer
• Pulse period measurement/pulse
width measurement
TBi IN
(i = 0 – 2)
Polarity selection
and edge pulse
generator
Event counter
fC32 (Note 1)
TB2 overflow
signal (Note 2)
Data bus (even)
(Low-order 8 bits)
(High-order 8 bits)
Reload register (16)
Counter (16)
Count start flag
(Address 4016)
Addresses
Timer B0 5116 5016
Timer B1 5316 5216
Timer B2 5516 5416
Counter reset
circuit
Notes 1. Clock source of clock timer; Only timer B2 can select it (refer to Fig. 65)
2. Only timer B1 can select it (internal connect mode)
Fig. 29 Timer B block diagram
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