M37733MHBXXXFP Datasheet, PDF (61/89 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
STANDBY FUNCTION
The WIT and the STP instructions make the microcomputer standby
state.
Table 10 shows the relationship between standby state and each
block’s operation.
When the WIT instruction is executed with the system clock stop bit
at wait state (bit 5 of the oscillation circuit control register 0) = “0”,
internal clock φ is stopped being at “L”, but the oscillation circuit,
system clock, and divided clocks f2 to f512 are not stopped.
Because divided clocks f2 to f512 are not stopped, a part of internal
peripheral devices which use these divided clocks can operate even
at wait state.
Otherwise, when the WIT instruction is executed with the system
clock stop bit at wait state = “1”, the oscillation circuit is not stopped,
but the system clock, divided clocks, and internal clock φ are stopped.
Accordingly, in this case, all of the internal peripheral devices which
use divided clocks f2 to f512, including the watchdog timer, are stopped.
When port-XC selection bit is “1” to operate the sub-clock oscillation
circuit, however, clock timer B2 can operate because clock fC32 for
the clock timer is not stopped.
When internal peripheral devices are not used, later wait state (System
clock stop bit at wait state = “1”) is more effective to restrict the current
consumption.
Make sure to set the system clock stop bit at wait state to “1”
immediately before the WIT instruction execution and clear the bit to
“0” immediately after the wait state is terminated.
The wait state is terminated when an interrupt request is accepted,
and the internal clock φ operation is restarted. At this time, interrupt
processing can immediately be executed because oscillation circuit’s
operation is not stopped during the wait state.
When the STP instruction is executed, the oscillation circuit is stopped
with internal clock φ stopped at “L”. Furthermore, “FFF16” is
automatically set into the watchdog timer, and the clock source of
the watchdog timer is forced to connect with f32 when the main clock
is selected or f8 when the sub clock is selected. This connection is
cut off when the most significant bit of the watchdog timer is cleared
to “0” or the microcomputer is reset, and the clock source is connected
with the input depending on the content of the watchdog timer
frequency selection flag. In the stop state, internal peripheral devices
using divided clocks f2 to f512 are stopped.
The stop state is terminated by system reset or interrupt request
acceptance, and then oscillation is restarted. At this time, supply of
system clock and divided clocks f2 to f512 is restarted.
In that condition, when the main clock external input selection bit is
“0” and the main clock is being selected as a system clock, or when
the sub clock external input selection bit is “0” and the sub clock is
being selected as a system clock, internal clock φ is stopped at “L” till
the most significant bit of the watchdog timer decremented with divided
clock f32 or f8 becomes “0”. However, supply of internal clock φ is
restarted immediately after the oscillation restarts by reset.
Accordingly, in this case, it is necessary to wait for the oscillation
stabilized before making the reset input “H”.
Otherwise in that condition, when the main clock external input
selection bit is “1” and the main clock is being selected as a system
clock, or when the sub clock external input selection bit is “1” and the
sub clock is being selected as a system clock, supply of internal clock
φ is restarted from the seventh clock of clock f2 after the oscillation
restarts. By this function, the microcomputer can immediately return
from the stop state when the clock supply input from the external is
stabilized.
Even though the main clock or the sub clock is input externally, make
sure to clear the main clock external input selection bit or the sub
clock external input selection bit to “0” before executing the STP
instruction if this external clock is unstable for a short time at a return
from the stop state.
Table 10. Relationship between standby state and each block’s operation
Instruction
System clock
stop bit at wait
state
Oscillation circuit
System clock
Operation at WIT/STP state
f2 – f512
Clock output φ 1 Internal clock φ ^{Internal peripheral devices}
using f2 – f512
“0”
Operating
(Note)
Operating
Operating
Operating
Stopped
(“L”)
Operation enabled
(Watchdog timer is operating)
WIT
“1”
Operating
(Note)
Stopped
Stopped
Stopped
(“L”)
Stopped
(“L”)
Operation disabled
(Watchdog timer is stopped)
(Clock timer’s operation is enabled)
STP
—
Stopped
Stopped
Stopped
Stopped
(“L”)
Stopped
(“L”)
Operation disabled
(Watchdog timer is stopped)
Note. When the main clock external input selection bit is “1”, the main clock oscillation circuit stops. When the sub clock external input selection
bit is “1”, the sub-clock oscillation circuit stops. (In both cases, the external clock can be input.)
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