M37733MHBXXXFP Datasheet, PDF (27/89 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode [01]
Figure 31 shows the bit configuration of the timer Bi mode register
during the event counter mode. In the event counter mode, the bit 0
of the timer Bi mode register must be “1” and bit 1 must be “0”.
The input signal from the TBiIN pin is counted when the count start
flag is “1”, and counting is stopped when it is “0”. Counting is performed
at the fall of the input signal when bits 2 and 3 are “0” and at the rise
of the input signal when bit 3 is “0” and bit 2 is “1”.
When bit 3 is “1” and bit 2 is “0”, counting is performed at the rise and
fall of the input signal.
When the sub-clock (32 kHz) oscillation circuit is used and others,
and the event counter mode is selected, timer B2 functions as the
clock timer and the original functions as timer B2 in the event counter
mode are lost. For details, refer to “(4) Clock timer”.
When the internal connect mode which connects timer B1 to timer
B2 is selected, the original function as timer B1 in the event counter
mode is lost. For details, refer to “(5) Internal connect mode”.
Data write, data read, and interrupt generation are performed in the
same way as for the timer mode.
(3) Pulse period measurement/pulse width
measurement mode [10]
Figure 32 shows the bit configuration of the timer Bi mode register
during the pulse period measurement/pulse width measurement
mode.
In the pulse period measurement/pulse width measurement mode,
bit 0 must be “0” and bit 1 must be “1”. Bits 6 and 7 are used to select
the clock source. The selected clock is counted when the count start
flag is “1”, and counting stops when it is “0”.
The pulse period measurement mode is selected when bit 3 is “0”. In
the pulse period measurement mode, the selected clock is counted
during the interval starting at the fall of the input signal from the TBiIN
pin to the next fall or at the rise of the input signal to the next rise.
And then, the result is stored in the reload register. In this case, the
reload register acts as a buffer register.
When bit 2 is “0”, the clock is counted from the fall of the input signal
to the next fall. When bit 2 is “1”, the clock is counted from the rise of
the input signal to the next rise.
In the case of counting from the fall of the input signal to the next fall,
counting is performed as follows. As shown in Figure 33, when the
fall of the input signal from TBiIN pin is detected, the contents of the
counter is transferred to the reload register. Next the counter is cleared
and count is started from the next clock. When the fall of the next
input signal is detected, the contents of the counter is transferred to
the reload register once more, the counter is cleared, and counting is
started. The period from the fall of the input signal to the next fall is
measured in this way.
After the contents of the counter is transferred to the reload register,
an interrupt request signal is generated and the interrupt request bit
of the timer Bi interrupt control register is set. However, no interrupt
request signal is generated when the contents of the counter is
transferred first time to the reload register after the count start flag is
set to “1”.
When bit 3 is “1”, the pulse width measurement mode is selected.
The pulse width measurement mode is similar to the pulse period
measurement mode except that the clock is counted from the fall of
the TBiIN pin input signal to the next rise or from the rise of the input
signal to the next fall as shown in Figure 34.
7 65 4 32 1 0
!0!!0 0
Addresses
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
5B16
5C16
5D16
0 0 : Always “00” in timer mode
! ! : Not used in timer mode and
may be any
0 : Always “0” in timer mode
(timer B0)
! :Not used in timer mode
(timers B1, B2)
! :Not used in timer mode
Clock source selection bit
0 0 : Select f2
0 1 : Select f16
1 0 : Select f64
1 1 : Select f512
Fig. 30 Timer Bi mode register bit configuration during timer mode
7 6 54 3 2 1 0
! !! 0
01
Addresses
Timer B0 mode register 5B16
Timer B1 mode register 5C16
Timer B2 mode register 5D16
0 1 : Always “01” in event counter
mode
0 0 : Count at the falling edge of input
signal
0 1 : Count at the rising edge of input
signal
1 0 : Count at the both falling edge and
rising edge of input signal
0 : Always “0” in event counter mode
(timer B0)
! : Not used in event counter mode
(timers B1, B2)
! ! ! : Not used in event counter mode
Fig. 31 Timer Bi mode register bit configuration during event counter
mode
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