M37733MHBXXXFP Datasheet, PDF (53/89 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Microprocessor mode [10]
Microprocessor mode is entered by connecting the CNVss pin to Vcc
and starting from reset. It can also be entered by programming the
processor mode bits to “10” after connecting the CNVss pin to Vss
and starting from reset. This mode is similar to the memory expansion
mode except that internal ROM is disabled and an external memory
is required, and clock φ 1 from port P42 is always output independently
of bit 7 of the processor mode register 0.
As shown in Table 7, φ 1 output can also be stopped with the signal
output disable selection bit “1”. In this case, write “1” to the port P42
direction register.
(4) Evaluation chip mode [11]
Evaluation chip mode is entered by applying voltage twice the VCC
voltage to the CNVSS pin. This mode is normally used for evaluation
tools.
The functions of E, ports P0 and P3 are the same as those in memory
expansion mode.
Port P1 functions as an address output pin while E is “H” and as data
I/O pin of odd addresses while E is “L” regardless of the BYTE pin
level.
Port P2 function as an address output pin while E is “H” and as data
I/O pin of even addresses while E is “L” when the BYTE pin level is
“L”.
When the BYTE pin level is “H” or 2·VCC, port P2 functions as an
address output pin while E is “H” and as data I/O pin of even and odd
addresses while E is “L”.
Port P4 and its data direction register which are located at address
0A16 and 0C16 are treated differently in evaluation chip mode. When
these addresses are accessed, the data bus width is treated as 16
bits regardless of the BYTE pin level, and the access cycle is treated
as internal memory regardless of the wait bit.
When a voltage twice the VCC voltage is applied to the BYTE pin, the
addresses corresponding to the internal ROM area are also treated
as 16-bit data bus.
The functions of ports P40 and P41 are the same as in memory
expansion mode.
Ports P42 to P46 become φ 1, MX, QCL, VDA, and VPA output pins
respectively. Port P47 becomes the DBC input pin.
φ 1 from port P42 is always output regardless of bit 7 of processor
mode register 0.
The MX signal normally contains the contents of flag m, however,
the contents of flag x is output when the CPU is using flag x.
QCL is the queue buffer clear signal. It becomes “H” when the
instruction queue buffer is cleared, for example, when a jump
instruction is executed.
VDA is the valid data address signal. It becomes “H” while the CPU
is reading data from data buffer or writing data to data buffer. It also
becomes “H” when the first byte of the instruction (operation code) is
read from the instruction queue buffer.
VPA is the valid program address signal. It becomes “H” while the
CPU is reading an instruction code from the instruction queue buffer.
DBC is the debug control signal and is used for debugging.
Table 8 shows the relationship between the CNVss pin input level
and the processor modes.
Table 8. Relationship between CNVss pin input levels and processor
modes
CNVss
Mode
Description
• Single-chip
Single-chip mode upon
• Memory expansion starting after reset. Each
Vss
• Microprocessor mode can be selected by
(• Evaluation chip) changing the processor
mode bits by software.
Vcc
• Microprocessor Microprocessor mode upon
(• Evaluation chip) starting after reset.
2·Vcc • Evaluation chip Evaluation chip mode only.
Table 7. Function of signal output disable selection bit CM6 (bit 6 of oscillation circuit control register 0)
Processor mode
Pin
CM6 = “0”
Function
CM6 = “1”
Single-chip mode
E
Enable signal E is output.
“L” is output.
E
E is output when the internal/external
E is output only when the external
memory area is accessed.
memory area is accessed.
Memory expansion mode,
Microprocessor mode
E
After WIT/STP instruction is executed,
“H” is output.
“L” is output after WIT/STP instruction is
executed.
∗ Standby state selection bit (bit 0 of port
function control register) must be set to
“1”.
“H”or “L” is output. (Output the content of
Microprocessor mode φ 1
Clock φ 1 is output independent of φ 1
output selection bit.
P42 latch.)
∗ Port P42 direction register must be set to
“1”.
Note. Functions shown in Table 7 cannot be emulated in a debugger. For the oscillation circuit control register 0, refer to Figure 63.
For the port function control register, refer to Figure 11.
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