M37733MHBXXXFP Datasheet, PDF (12/89 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
INTERRUPTS
Table 1 shows the interrupt sources and the corresponding interrupt
vector addresses. Reset is also treated as a source of interrupt and
is described in this section.
DBC is an interrupt used only for debugging.
Interrupts other than reset, DBC, watchdog timer, zero divide, and
BRK instruction all have their respective interrupt control registers.
Table 2 shows the addresses of the interrupt control registers and
Figure 6 shows the bit configuration of the interrupt control register.
The interrupt request bit is automatically cleared by hardware during
reset or when processing an interrupt. Also, interrupt request bits
other than DBC and watchdog timer can be cleared by software.
INT0 to INT2 are external interrupts, and whether to cause an interrupt
at the input level (level sense) or at the edge (edge sense) can be
selected with the level sense/edge sense selection bit. Furthermore,
the polarity of the interrupt input can be selected with a polarity
selection bit.
In the INT2 /Key input interrupt, whether to input an interrupt request
from the INT2 pin or the KI0 – KI3 pins can be selected by bit 7 of the
port function control register (refer to Figure 11).
Timer and UART interrupts are described in the respective section.
The priority of interrupts when multiple interrupts are caused
simultaneously is partially fixed by hardware, but it can also be
adjusted by software as shown in Figure 7. The hardware priority is
fixed as follows:
reset > DBC > watchdog timer > other interrupts
Table 1. Interrupt sources and the interrupt vector addresses
Interrupts
A-D/UART2 trans./rece.
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT2 /Key input
INT1
INT0
Watchdog timer
DBC (unusable)
BRK instruction
Zero divide
Reset
Vector addresses
00FFD616 00FFD716
00FFD816 00FFD916
00FFDA16 00FFDB16
00FFDC16 00FFDD16
00FFDE16 00FFDF16
00FFE016 00FFE116
00FFE216 00FFE316
00FFE416 00FFE516
00FFE616 00FFE716
00FFE816 00FFE916
00FFEA16 00FFEB16
00FFEC16 00FFED16
00FFEE16 00FFEF16
00FFF016 00FFF116
00FFF216 00FFF316
00FFF416 00FFF516
00FFF616 00FFF716
00FFF816 00FFF916
00FFFA16 00FFFB16
00FFFC16 00FFFD16
00FFFE16 00FFFF16
7 6 54 3 21 0
Interrupt priority level selection bits
Interrupt request bit
0 : No interrupt
1 : Interrupt
Interrupt control register configuration for timers A0 to A4, timers B0 to B2, UART0, UART1 and
A-D/UART2 trans./rece.
7 6 54 3 21 0
Interrupt priority level selection bits
Interrupt request bit
0 : No interrupt
1 : Interrupt
Polarity selection bit
0 : Interrupt request bit is set at “H” level for level sense or at the falling
edge for edge sence.
1 : Interrupt request bit is set at “L” level for level sense or at the rising
edge for edge sense.
Level sense/edge sense selection bit
0 : Edge sense
1 : Level sense
Interrupt control register configuration for INT0 to INT2/Key input
Fig. 6 Interrupt control register bit configuration
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