M37733MHBXXXFP Datasheet, PDF (36/89 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When the transmission register becomes empty after its contents
has been transmitted, data is automatically transferred from the
transmission buffer register to the transmission register if the next
transmission start condition is satisfied. If bit 2 of the UARTj transmit/
receive control register 0 is “1”, CTSj input is ignored and transmission
start is controlled only by the TEj flag and TIj flag. Once transmission
has started, the TEj flag, TIj flag, and CTSj signals are ignored until
data transmission completes. Therefore, transmission is not interrupt
even when CTSj input is changed to “H” during transmission.
As shown in Figure 42, CTSj and flags TEj and TIj, which indicate the
transmission start condition, are checked while the TENDj signal is
“H”. Therefore, data can be transmitted continuously if the next
transmission data is written in the transmission buffer register and
the TIj flag is cleared to “0” before the TENDj signal level becomes H”.
The bit 3 (TXEPTYj flag) of the UARTj transmit/receive control register
0 changes to “1” at the next cycle after the TENDj signal level becomes
“H”. Furthermore, the TxEPTYj flag changes to “0” when transmission
starts. Therefore, this flag can be used to determine whether data
transmission has been completed.
When the TIj flag changes from “0” to “1”, the interrupt request bit in
the UARTj transmission (transmit/receive in UART2) interrupt control
register is set to “1”.
Since UART0 has three output pins (CLK0, CLKS0, and CLKS1) for
the transmission clock, the user can select one from these pins when
using the internal clock. Accordingly, data can be transmitted to three
external receive devices which will not receive data at the same time.
Figure 43 shows the extrnal connection diagram example.
To select the transmission clock output multiple-selection mode, it is
necessary to set bits 5 and 4 of the serial transmit control register. In
addition, it is necessary to select the internal clock, to disable CTS
and RTS, and disable reception, with the UART0 transmit/receive
mode register and the UART0 transmit/receive control register 0/1.
Figure 44 shows the bit configuration of the serial transmit control
register and Figure 45 shows the bit configuration of the UART0
transmit/receive mode register and the UART0 transmit/receive
control register 0/1 in the transmission clock output multiple-selection
mode. Furthermore, Table 6 shows the function of bits 5 and 4
(Transmission clock output pin selection bits, TC1 and TC0) of the
serial transmit control register. As shown in Table 5, the transmission
clock is output from the CLK0, CLKS0, or CLKS1 pin depending on
TC1, TC0. Do not change the value of TC1 and TC0 during transferring.
The transmission clock polarity also depends on bit 6 (CPL) of the
UART0 transmit/receive control register 0.
76 543 21 0
TC1 TC0
Serial transmit
control register
Adress
6E16
Transmission clock output pin selection bits
0 0 : Normal mode
(Clock is output only from CLK0)
0 1 : Multiple clocks are specified
(Clock is output from CLK0)
1 0 : Multiple clocks are specified
(Clock is output from CLKS0)
1 1 : Multiple clocks are specified
(Clock is output from CLKS1)
Fig. 44 Bit configuration of serial transmit control register
Table 6. Relationship between transmission clock output pin selection
bits and pin functions
Transmission clock
output pin selection bits
TC1
TC0
P81
CLK0
P82
RXD0
CLKS0
P80
CTS0/RTS0
CLKS1
0
0
CLK0 RXD0
P8/CTS0/RTS0
0
1
CLK0 “H” (Note2)
P80
1
0
“H” CLKS0
P80
1
1
“H” “H” (Note2)
CLKS1
Notes 1. In this table, the CLK polarity selection bit (CPL) is “0”.
When CPL is “1”, “H” in this table becomes “L”. The polarity
of CLK0, CLKS0, or CLKS1 also depends on CPL.
2. When bit 2 of the port P8 direction register is “1”, “H” is
output. When this bit is “0”, floating is entered.
UART 0
TXD0
CLKS1
CLKS0
CLK0
DIN
DIN
DIN
CLK
CLK
CLK
Note. Clock synchronous serial I/O communication and internal clock are used.
This connection is applied only in transmission mode.
Fig. 43 External connection diagram example in the transmission clock output multiple-selection mode
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