M37733MHBXXXFP Datasheet, PDF (55/89 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
Figures 63 and 65 show the bit configuration of the oscillation circuit
control registers 0, 1 and the clock generating circuit diagram. The
clock generating circuit consists of main- and sub-clock oscillation
circuits, system clock switch circuit, clock dividing circuit, standby
control circuit, and others. The oscillation circuit control registers are
some of the control registers for the clock generating circuit.
Clocks φ , f2 to f512, fC32, and φ 1 are used in CPU and internal
peripheral devices or are output from pins, and they are made of the
main or sub clock, as shown in Figure 65.
The system clock and the clock f2 can be switched to high-speed
clocks or low-speed clocks shown in Table 9. When using the sub
clock, it is possible to select one of 3 types: the main clock divided by
2, the direct main clock (not divided) and the sub clock divided by 2
as the clock f2.
When not using the sub clock, it is possible to select one of 4 types:
the main clock divided by 2, divided by 8, divided by 16 and the direct
main clock (not divided) as the clock f2.
This function of clocks switch make it possible to adapt power control
to the system operation.
Bits 0 to 4 of the oscillation circuit control register 0 and bit 0 of the
oscillation circuit control register 1 control sub-clock oscillation start,
system clock selection, stop/restart of main-clock oscillation, sub-
clock drivability selection and the main clock division selection.
The method of clocks switch is described bellow.
When selecting the main clock as the system clock, the main clock
division selection bit (bit 0 of the oscillation circuit control register 1)
selects either the main clock divided by 2 or the direct main clock as
the clock f2. When this bit is “1”, the clock f2 is the direct main clock
which is not divided, so that a half external input frequency is enough
to perform the same operation speed. Consequently, power
dissipation could be conserved (refer to Figure 69.) The main clock
division selection bit is valid regardless of either using the sub clock
or not.
Figure 66 shows the system clock state transition when using the
sub clock.
From the time during reset to the time reset is released, only the
main clock, which is selected as the system clock, oscillates.
If the port-XC selection bit is set to “1” in this term, the sub-clock
oscillation circuit starts oscillation. When the sub clock is not used,
fix the port-XC selection bit to “0” (“0” at reset) and use the P77/AN7
XCIN and P76/AN6/XCOUT pins as I/O ports P77 and P76 or analog
inputs AN7 and AN6, respectively.
Table 9. Selection of system clock and clock f2
Sub clock
Not used
Used
Port-Xc
selection bit
(CM4)
0
0
0
0
1
1
1
1
System clock
selection bit
(CM3)
0
0
1
1
0
0
1
1
Main clock
division selection
bit (CC0)
0
1
0
1
0
1
0
1
System clock
Main clock
Main clock
Main clock divided by 8
Main clock divided by 8
Main clock
Main clock
Sub clock
Sub clock
Clock f2
Main clock divided by 2
Main clock
Main clock divided by 16
Main clock divided by 8
Main clock divided by 2
Main clock
Sub clock divided by 2
Sub clock divided by 2
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