M37733MHBXXXFP Datasheet, PDF (44/89 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
The watchdog timer is used to detect unexpected execution sequence
caused by software runaway.
Figure 51 shows a block diagram of the watchdog timer. The watchdog
timer includes a 12-bit binary counter.
The watchdog timer counts divided clock f32 or f512. Whether to count
f32 or f512 is determined by the watchdog timer frequency selection
flag shown in Figure 52. For divided clocks f32 and f512, refer to the
section on clock generating circuit. f512 is selected when the flag is
“0” and f32 is selected when it is “1”. The flag is cleared after reset.
“FFF16” is set in the watchdog timer when “L” or 2 Vcc is applied to
the RESET pin, STP instruction is executed, data is written to the
watchdog timer register, or the most significant bit of the watchdog
timer becomes “0”.
After “FFF16” is set in the watchdog timer, the contents of the watchdog
timer is decremented by one at every cycle of f32 or f512. After 2048
counts, the most significant bit of the watchdog timer becomes “0”,
and a watchdog timer interrupt request bit is set, and “FFF16” is set in
the watchdog timer.
Normally, a program is written so that data is written in the watchdog
timer register before the most significant bit of the watchdog timer
becomes “0”. If this routine is not executed due to unexpected program
runaway, the most significant bit of the watchdog timer becomes
eventually “0” and an interrupt is generated.
The processor can be reset by setting “1” to the software reset bit (bit
3 of the processor mode register 0) described in Figure 10 on the
interrupt section and generating a reset pulse.
The watchdog timer stops its function when the RESET pin voltage is
raised to double the Vcc voltage.
The watchdog timer can also be used to recover from when the clock
is stopped by the STP instruction. Refer to the section on stand-by
function for more details.
The watchdog timer hold the contents during a hold state and the
input of the divided clock is stopped.
Select with the watchdog timer frequency selection flag.
(If STP instruction is executed, f32 is forced to be selected when
the system clock selection bit is “0”, or f8 is forced to be selected
when the system clock selection bit is “1”.)
f32
f512
Hold
Write to watchdog
timer register
Watchog timer
(Address 6016)
RESET
2 • Vcc
detection
circuit
Set “FFF16”
STP instruction _{S Q}
R
(Note)
Note. When the main clock external input selection bit is “1”
and the main clock or the main clock divided by 8 is
selected as a system clock, or the sub-clock external
input selection bit is “1” and the sub-clock is selected;
the divided clock f16 is input.
Fig. 51 Watchdog timer block diagram
7 6 5 4 3 21 0
Watchdog timer
frequency
selection flag
Addresses
6116
0 : Select f512
1 : Select f32
Fig. 52 Watchdog timer frequency selection flag
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