M37733MHBXXXFP Datasheet, PDF (21/89 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Furthermore, in the event counter mode, whether to increment or
decrement the counter can also be determined by supplying two kinds
of pulses of which phases differ by 90° to timer A2, A3, or A4. There
are two types of two-phase pulse signal processing operations. One
uses timer A2 and the other uses timer A4. Timer A3 can select one
of these two operations with bit 7 of the timer A3 mode register. In
both processing operations, two kinds of pulses of which phases differ
by 90° are input to the TAjOUT (j = 2 to 4) pin and TAjIN pin respectively.
After the level of the TA2OUT pin changes from “L” to “H” with timer
A2 used, as shown in Figure 19, the count is incremented when a
rising edge is input to the TA2IN pin and the count is decremented
when the falling edge is input.
For timer A4, as shown in Figure 20, when a phase related pulse
with a rising edge input to the TA4IN pin is input after the level of
TA4OUT pin changes from “L” to “H”, the count is incremented at the
respective rising edge and falling edge of the TA4OUT pin and TA4IN
pin. When a phase related pulse with a falling edge input to the TA4OUT
pin is input after the level of TA4IN pin changes from “H” to “L”, the
count is decremented at the respective rising edge and falling edge
of the TA4IN pin and TA4OUT pin.
When performing this two-phase pulse signal processing, bits 0 and
4 of the timer Aj mode register must be set to “1” and bits 1, 2, 3, and
5 must be set to “0” as shown in Figure 21.
Bit 7 is used to select whether to perform two-phase pulse signal
processing for timer A3 in the same manner as timer A2 or as timer
A4. When this bit is “0”, two-phase pulse signal processing for timer
A3 is performed in the same manner as timer A2 and when it is “1”, it
is performed in the same manner as timer A4. This bit is ignored for
timers A2 and A4.
Note that bits 5, 6, and 7 of the up-down flag (address 4416) are the
two-phase pulse signal processing selection bits for timers A2, A3,
and A4, respectively.
Each timer operates in the normal event counter mode when the
corresponding bit is “0” and performs two-phase pulse signal
processing when it is “1”.
Count is started by setting the count start flag to “1”. Data write and
read are performed in the same way as for the normal event counter
mode. Note that the port direction register of the input port must be
set to the input mode because two-phase pulse signal is input. Also,
there can be no pulse output in this mode.
TA2OUT
TA2IN
Increment Increment Increment Decrement Decrement Decrement
count
count
count
count
count
count
Fig. 19 Two-phase pulse signal processing operation of timer A2
TA4OUT
Increment count at each edge Decrement count at each edge
TA4IN
Increment count at each edge Decrement count at each edge
Fig. 20 Two-phase pulse signal processing operation of timer A4
7 6 54 3 21 0
01 0 00 1
Addresses
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
5816
5916
5A16
0 1 : Always “01” in event counter
mode
0 1 0 0 : Always “0100” when processing
two-phase pulse signal
0 : Reload
1 : No reload
This bit is avilable for timer A3
0 : Two-phase pulse signal processing
in the same manner as timer A2
1 : Two-phase pulse signal processing
in the same manner as timer A4
Fig. 21 Timer Aj mode register bit configuration when performing
two-phase pulse signal processing in event counter mode
21