M37733MHBXXXFP Datasheet, PDF (20/89 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode [01]
Figure 17 shows the bit configuration of the timer Ai mode register
during the event counter mode. In the event counter mode, the bit 0
of the timer Ai mode register must be “1” and bits 1 and 5 must be
“0”.
The input signal from the TAiIN pin is counted when the count start
flag shown in Figure 15 is “1” and counting is stopped when it is “0”.
Count is performed at the fall of the input signal when bit 3 is “0” and
at the rise of the signal when it is “1”.
In the event counter mode, whether to increment or decrement the
count can be selected with the up-down flag or the input signal from
the TAiOUT pin.
When bit 4 of the timer Ai mode register is “0”, the up-down flag is
used to determine whether to increment or decrement the count
(decrement when the flag is “0” and increment when it is “1”). Figure
18 shows the bit configuration of the up-down flag.
When bit 4 of the timer Ai mode register is “1”, the input signal from
the TAiOUT pin is used to determine whether to increment or decrement
the count. However, note that bit 2 must be “0” if bit 4 is “1”. Because
TAiOUT pin becomes an output pin with pulse output if bit 2 is “1”.
The count is decremented when the input signal from the TAiOUT pin
is “L” and incremented when it is “H”. Determine the level of the input
signal from the TAiOUT pin before an effective edge is input to the
TAiIN pin.
An interrupt request signal is generated and the interrupt request bit
of the timer Ai interrupt control register is set when the counter reaches
000016 (decrement count) or FFFF16 (increment count). At the same
time, timers A0 and A1 transfer the contents of the reload register to
the counter and continue counting.
Timers A2, A3, and A4 transfer the contents of the reload register to
the counter and continue count when bit 6 of the corresponding timer
Ai mode register is “0”, but when bit 6 is “1”, they continue counting
without transferring the contents of the reload register to the counter.
When bit 2 is “1”, the waveform of which polarity is reversed each
time the counter reaches 000016 (decrement count) or FFFF16
(increment count) is output from TAiOUT pin. If bit 2 is “0”, the TAiOUT
pin can be used as a normal port pin. However, if bit 4 is “1” and the
TAiOUT pin is used as an output pin, the output from the TAiOUT pin
changes the count direction. Therefore, bit 4 must be “0” unless the
output from the TAiOUT pin is used to select the count direction.
Data write and data read are performed in the same way as for the
timer mode. That is, when data is written to timer Ai which is halted,
it is also written to the reload register and the counter.
When data is written to timer Ai which is busy, the data is written to
the reload register, but not the counter. The counter is reloaded with
new data from the reload register at the next reload time and continues
counting. For timers A2, A3, and A4, the contents of the reload register
is not reloaded in the counter when bit 6 of the corresponding timer
Ai mode register is “1”. The contents of the counter can be read at
any time.
76 5 43 2 10
0
01
Addresses
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
5616
5716
5816
5916
5A16
0 1 : Always “01” in event counter
mode
0 : No pulse output
1 : Pulse output
0 : Count at the falling edge of input
signal
1 : Count at the rising edge of input
signal
0 : Increment or decrement according
to up-down flag
1 : Increment or decrement according
to TAiOUT pin input signal level
0 : Always “0” in event counter mode
This bit is available for times A2, A3,
and A4.
0 : Reload
1 : No reload
This bit is available for timer A3.
0 : Two-phase pulse signal processing
in the same manner as timer A2
1 : Two-phase pulse signal processing
in the same manner as timer A4
Fig. 17 Timer Ai mode register bit configuration during event counter
mode
76 5 43 2 10
Up-down flag
Addresses
4416
Timer A0 up-down flag
Timer A1 up-down flag
Timer A2 up-down flag
Timer A3 up-down flag
Timer A4 up-down flag
Timer A2 two-phase pulse signal processing
selection bit
0 : Two-phase pulse signal processing disabled
1 : Two-phase pulse signal processing mode
Timer A3 two-phase pulse signal processing
selection bit
0 : Two-phase pulse signal processing disabled
1 : Two-phase pulse signal processing mode
Timer A4 two-phase pulse signal processing
selection bit
0 : Two-phase pulse signal processing disabled
1 : Two-phase pulse signal processing mode
Fig. 18 Up-down flag bit configuration
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