M37733MHBXXXFP Datasheet, PDF (60/89 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When the port-XC selection bit is set to “1” to use sub-clock oscillation
and timer B2 is set to be in the event count mode, clock fC32 which is
the sub clock (32 kHz) divided by 32 is selected as the count source
of timer B2. By this selection, timer B2 can be used as the clock
timer. For setting of timer B2 related registers, refer to the section on
clock timer mode of timer B2.
The clock prescaler in which the sub clock is divided by 32 is reset by
writing “1”, in dummy, into bit 7 (clock prescaler reset bit) of the
oscillation circuit control register 1.
When the main clock is selected, by this function, clock fC32 of clock
timer B2 can be synchronized with software. Figure 68 shows the
operation timing for clock prescaler and clock timer B2.
Figure 69 shows the clock f2 state transition when the port-Xc selection
bit is “0” and the sub clock is not used.
From the time during reset to the time reset is released, the main
clock divided by 2 is being selected as the clock f2. When the system
clock selection bit is set “1” in that condition, the main clock divided
by 16 is selected as the clock f2 and the clock frequency supplied for
the CPU and internal peripheral devices is divided by 8 more. It makes
current consumption restrict, although the operation speed slows.
When the timer B2 clock source selection bit (bit 1 of the port function
control register) is set to “1” and event counter mode is selected in
timer B2 under the condition which the port-Xc selection bit is “0”;
fc32, which is the main clock divided by 32, is connected as a timer
B’s count source. Accordingly, timer B2 can be used as a clock timer
which always operates with a regular clock source shown in Figure
69. For details relating to register setting of timer B2, refer to the
section “Clock timer” on timer B.
Timer B2 count start flag
Writing pulse of clock
prescaler reset bit
XCIN
Clock source of clock timer(fc32)
XCIN × 31(cycle)^(Note)
XCIN × 32 (cycle)
Timer B2 count value
n (Set value)
n–1
This applies when the main clock is selected as the system clock (System clock selection bit (CM3) = “0”).
Note. Period of fc32 = XCIN × 31 (cycle) (only in this term)
Period of fc32 = XCIN × 32 (cycle) (after this term)
Fig. 68 Operation timing for clock prescaler and clock timer B2
CC0 = “1”
Reset
(Note 1)
f2 = f(XIN) / 2
Notes 1. f2 = f(XIN) / 2 expresses that the clock f2 is
the main clock divided by 2.
2. f2 = f(XIN) expresses that the clock f2 is the
direct main clock, which is not divided.
CM3 = “0”
(Note 12)
f2f2= =f(Xf(IXNI)N/) 2
CC0 = “0”
CM3 = “0”
CM3 = “1”
CC0 = “1”
f2 = f(XIN) / 16
CM3 = “1”
f2 = f(XIN) / 8
• In the case of not using sub clock (CM4 = “0”)
CC0 = “0”
CC0 = Main clock division selection bit
CM3 = System clock selection bit
CM4 = Port-Xc selection bit
Fig. 69 Clock f2 state transition (when the sub clock is not used.)
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