M37733MHBXXXFP Datasheet, PDF (8/89 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
STACK POINTER (S)
Stack pointer (S) is a 16-bit register. It is used during a subroutine
call or interrupts. It is also used during stack, stack pointer relative,
or stack pointer relative indirect indexed Y addressing modes.
PROGRAM COUNTER (PC)
Program counter (PC) is a 16-bit counter that indicates the low-order
16 bits of the next program memory address to be executed. There
is a bus interface unit between the program memory and the CPU,
so that the program memory is accessed through the bus interface
unit. This is described later.
PROGRAM BANK REGISTER (PG)
Program bank register (PG) is an 8-bit register that indicates the high-
order 8 bits of the next program memory address to be executed.
When a carry occurs by incrementing the contents of the program
counter, the contents of the program bank register (PG) is incremented
by 1. Also, when a carry or borrow occurs after adding or subtracting
the offset value to or from the contents of the program counter (PC)
by using a branch instruction, the contents of the program bank
register (PG) is incremented or decremented by 1 so that programs
can be written without worrying about bank boundaries.
DATA BANK REGISTER (DT)
Data bank register (DT) is an 8-bit register. With some addressing
modes, a part of the data bank register (DT) is used to specify a
memory address. The contents of data bank register (DT) is used as
the high-order 8 bits of a 24-bit address. Addressing modes that use
the data bank register (DT) to specify the address are direct indirect,
direct indexed X indirect, direct indirect indexed Y, absolute, absolute
bit, absolute indexed X, absolute indexed Y, absolute bit relative,
and stack pointer relative indirect indexed Y.
DIRECT PAGE REGISTER (DPR)
Direct page register (DPR) is a 16-bit register. Its contents is used as
the base address of a 256-byte direct page area. The direct page
area is allocated in bank 016, but when the contents of DPR is FF0116
or more, the direct page area spans across bank 016 and bank 116.
All direct addressing modes use the contents of the direct page register
(DPR) to generate the data address. If the low-order 8 bits’ contents
of the direct page register (DPR) is “0016”, the number of cycles
required to generate an address is minimized. Hence the low-order 8
bits’ contents of the direct page register (DPR) is usually set to “0016”.
PROCESSOR STATUS REGISTER (PS)
Processor status register (PS) is an 11-bit register. It consists of flags
which indicate the result of operation and the processor interrupt
priority level (IPL).
Branch operations can be performed by testing flags C, Z , V, and N.
The details of each processor status register bit are described below.
1. Carry flag (C)
The carry flag contains the carry or borrow generated by the ALU
after an arithmetic operation. This flag is also affected by shift or
rotate instruction. This flag can be set or reset directly with the SEC,
CLC instructions or with the SEP, CLP instructions.
2. Zero flag (Z)
This zero flag is set when the result of an arithmetic operation or data
transfer is zero and reset when it is not. This flag can be set or reset
directly with the SEP or CLP instruction.
3. Interrupt disable flag ( I )
When the interrupt disable flag is “1”, all interrupts except watchdog
timer, DBC, and software interrupt are disabled. This flag is
automatically set to “1” when an interrupt is accepted. It can be set or
reset directly with the SEI, CLI instructions or SEP and CLP
instructions.
4. Decimal mode flag (D)
The decimal mode flag determines whether addition and subtraction
are performed in the binary or the decimal system. Binary arithmetic
is performed when this flag is “0”. If it is “1”, decimal arithmetic is
performed with each word treated as the 2- or 4-digit number.
Arithmetic operation is performed with 4-digit number when the data
length flag (m) is “0” and with 2-digit number when it is “1”. Decimal
correction is automatically performed. (Decimal operation is possible
only with the ADC and SBC instructions.) This flag can be set or
reset with the SEP or CLP instruction.
5. Index register length flag (x)
The index register length flag determines whether index register X
and index register Y are used as 16-bit registers or as 8-bit registers.
The registers are used as 16-bit registers when flag x is “0” and as 8-
bit registers when it is “1”. This flag can be set or reset with the SEP
or CLP instruction.
6. Data length flag (m)
The data length flag determines whether the data has a length of 16
bits or that of 8 bits. The 16-bit length is selected when flag m is “0”
and the 8-bit length is selected when it is “1”. This flag can be set or
reset with the SEM, CLM instructions or with the SEP, CLP
instructions.
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