PIC16F753 Datasheet, PDF (94/238 Pages) Microchip Technology – 14/16-Pin, Flash-Based 8-Bit CMOS Microcontrollers

PIC16F753/HV753
11.4 Output Control
Upon disabling, or immediately after enabling the COG
module, the complementary drive is configured with
COGxOUT0 drive inactive and COGxOUT1 drive
active.
11.4.1 OUTPUT ENABLES
Each COG output pin has an individual output enable
control. Output enables are selected with the GxOE0 and
GxOE1 bits of the COGxCON0 register (Register 11-1).
When an output enable control is cleared, the module
asserts no control over the pin. When an output enable is
set, the override value or PWM waveform is applied to
the pin per the port priority selection.
The device pin output enable control bits are
independent of the GxEN bit of the COGxCON0
register, which enables the COG. When GxEN is
cleared, and shutdown is not active, the Reset state
PWM levels are present on the COG output pins. The
PWM levels are affected by the polarity controls. If
shutdown is active when GxEN is cleared, the
shutdown override levels will be present on the COG
output pins. Note that setting the GxASE bit while the
GxEN bit is cleared will activate shutdown which can
only be cleared by either a rising event while the GxEN
bit is set, or a device Reset.
11.4.2 POLARITY CONTROL
The polarity of each COG output can be selected
independently. When the output polarity bit is set, the
corresponding output is active-low. Clearing the output
polarity bit configures the corresponding output as
active-high. However, polarity does not affect the
shutdown override levels.
Output polarity is selected with the GxPOL0 and
GxPOL1 bits of the COGxCON0 register (Register 11-1).
11.5 Dead-Band Control
The dead-band control provides for non-overlapping
PWM output signals to prevent shoot-through current
in the external power switches.
The COG contains two dead-band timers. One
dead-band timer is used for rising event dead-band
control. The other is used for falling event dead-band
control. Timer modes are selectable as either:
• Asynchronous delay chain
• Synchronous counter
The dead-band Timer mode is selected for the
COGxOUT0 and COGxOUT1 dead-band times with
the respective GxRDBTS and GxFDBTS bits of the
COGxCON1 register (Register 11-2).
11.5.1
ASYNCHRONOUS DELAY CHAIN
DEAD-BAND DELAY
Asynchronous dead-band delay is determined by the
time it takes the input to propagate through a series of
delay elements. Each delay element is a nominal five
nanoseconds.
Set the COGxDBR register (Register 11-9) value to the
desired number of delay elements in the COGxOUT0
dead band. Set the COGxDBF register (Register 11-10)
value to the desired number of delay elements in the
COGxOUT1 dead band. When the value is zero,
dead-band delay is disabled.
11.5.2
SYNCHRONOUS COUNTER
DEAD-BAND DELAY
Synchronous counter dead band is timed by counting
COG_clock periods from zero up to the value in the
dead-band count register. Use Equation 11-1 to
calculate dead-band times.
Set the COGxDBR count register value to obtain the
desired dead-band time of the COGxOUT0 output. Set
the COGxDBF count register value to obtain the
desired dead-band time of the COGxOUT1 output.
When the value is zero, dead-band delay is disabled.
11.5.3
SYNCHRONOUS COUNTER
DEAD-BAND TIME UNCERTAINTY
When the rising and falling events that trigger the
dead-band counters come from asynchronous inputs,
it creates uncertainty in the synchronous counter
dead-band time. The maximum uncertainty is equal to
one COG_clock period. Refer to Equation 11-1 for
more detail.
When event input sources are asynchronous with no
phase delay, use the asynchronous delay chain
dead-band mode to avoid the dead-band time
uncertainty.
DS40001709A-page 94
Preliminary
 2013 Microchip Technology Inc.