PIC16F753 Datasheet, PDF (77/238 Pages) Microchip Technology – 14/16-Pin, Flash-Based 8-Bit CMOS Microcontrollers

PIC16F753/HV753
9.0 HARDWARE LIMIT TIMER (HLT)
MODULE
The Hardware Limit Timer (HLT) module is a version of
the Timer2-type modules. In addition to all the Timer2-
type features, the HLT can be reset on rising and falling
events from selected peripheral outputs.
The HLT primary purpose is to act as a timed hardware
limit to be used in conjunction with asynchronous
analog feedback applications. The external Reset
source synchronizes the HLTMRx to an analog
application.
In normal operation, the external Reset source from the
analog application should occur before the HLTMRx
matches the HLTPRx. This resets HLTMRx for the next
period and prevents the HLTimerx Output from going
active.
When the external Reset source fails to generate a
signal within the expected time, (allowing the HLTMRx
to match the HLTPRx), then the HLTimerx Output
becomes active.
FIGURE 9-1:
HLTMRx BLOCK DIAGRAM
The HLT module incorporates the following features:
• 8-bit Read-Write Timer Register (HLTMRx)
• 8-bit Read-Write Period register (HLTPRx)
• Software programmable prescaler:
- 1:1
- 1:4
- 1:16
- 1:64
• Software programmable postscaler
- 1:1 to 1:16, inclusive
• Interrupt on HLTMRx match with HLTPRx
• Eight selectable timer Reset inputs (two reserved)
• Reset on rising and falling event
Refer to Figure 9-1 for a block diagram of the HLT.
CCP1 out 000
C1OUT 001
C2OUT 010
COG1FLT 011
COG1OUT0 100
COG1OUT1 101
‘0’ 110
‘0’ 111
HxREREN
HxFEREN
HxRES
Detect
1
0
0
Detect
1
HxFES
HLT Output
To COG module
Fosc/4
HxON
Prescaler
1:1, 1:4, 1:16, 1:64
HxCKPS<1:0>
HLTMRx
Comparator
HLTPRx
Postscaler
1:1 to 1:16
HxOUTPS<3:0>
HLTMRxIF
 2013 Microchip Technology Inc.
Preliminary
DS40001709A-page 77