PIC16F753 Datasheet, PDF (78/238 Pages) Microchip Technology – 14/16-Pin, Flash-Based 8-Bit CMOS Microcontrollers

PIC16F753/HV753
9.1 HLT Operation
The clock input to the HLT module is the system
instruction clock (FOSC/4). HLTMRx increments on
each rising clock edge.
A 4-bit counter/prescaler on the clock input provides the
following prescale options:
• Direct input
• Divide-by-4
• Divide-by-16
• Divide-by-64
The prescale options are selected by the prescaler
control bits, HxCKPS<1:0> of the HLTxCON0 register.
The value of HLTMRx is compared to that of the Period
register, HLTPRx, on each clock cycle. When the two
values match,then the comparator generates a match
signal as the HLTimerx output. This signal also resets
the value of HLTMRx to 00h on the next clock rising
edge and drives the output counter/postscaler (see
Section 9.2 “HLT Interrupt”).
The HLTMRx and HLTPRx registers are both directly
readable and writable. The HLTMRx register is cleared
on any device Reset, whereas the HLTPRx register
initializes to FFh. Both the prescaler and postscaler
counters are cleared on any of the following events:
• A write to the HLTMRx register
• A write to the HLTxCON0 register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESET Instruction
Note: HLTMRx is not cleared when HLTxCON0 is
written.
9.2 HLT Interrupt
The HLT can also generate an optional device interrupt.
The HLTMRx output signal (HLTMRx-to-HLTPRx match)
provides the input for the 4-bit counter/postscaler. The
overflow output of the postscaler sets the HLTMRxIF bit
of the PIR1 register. The interrupt is enabled by setting
the HLTMRx Match Interrupt Enable bit, HLTMRxIE of
the PIE1 register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, HxOUTPS<3:0>, of the HLTxCON0 register.
9.3 Peripheral Resets
Resets driven from the selected peripheral output pre-
vents the HLTMRx from matching the HLTPRx register
and generating an output. In this manner, the HLT can
be used as a hardware time limit to other peripherals.
In this device, the primary purpose of the HLT is to limit
the COG PWM duty cycle. Normally, the COG opera-
tion uses analog feedback to determine the PWM duty
cycle. The same feedback signal is used as an HLT
Reset input. The HLTPRx register is set to occur at the
maximum allowed duty cycle. If the analog feedback to
the COG exceeds the maximum time, then an
HLTMRx-to-HLTPRx match will occur and generate the
output needed to limit the COG drive output.
The HLTMRx can be reset by one of several selectable
peripheral sources. Reset inputs include:
• CCP1 output
• Comparator 1 output
• Comparator 2 output
• COGxFLT pin
• COG1OUT0
• COG1OUT1
The external Reset input is selected with the
HxERS<2:0> bits of the HLTxCON1 register. High and
low Reset enables are selected with the HxREREN and
HxFEREN bits, respectively. Setting the HxRES and
HxFES bits makes the respective rising and falling
Reset events edge sensitive. Reset inputs that are not
edge sensitive are level sensitive.
HLTMRx Resets are synchronous with the HLT clock.
In other words, HLTMRx is cleared on the rising edge
of the HLT clock after the enabled Reset event occurs.
If an enabled external Reset occurs at the same time a
write occurs to the TMR4A register, the write to the
timer takes precedence and pending Resets are
cleared.
9.4 HLTimerx Output
The unscaled output of HLTMRx is available only to the
COG module, where it is used as a selectable limit to
the maximum COG period.
9.5 HLT Operation During Sleep
The HLT cannot be operated while the processor is in
Sleep mode. The contents of the HLTMRx register will
remain unchanged while the processor is in Sleep
mode.
DS40001709A-page 78
Preliminary
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