PIC16F753 Datasheet, PDF (136/238 Pages) Microchip Technology – 14/16-Pin, Flash-Based 8-Bit CMOS Microcontrollers

PIC16F753/HV753
15.4.1 COMPARATOR OUTPUT
SYNCHRONIZATION
The output from either comparator, C1 or C2, can be
synchronized with Timer1 by setting the CxSYNC bit of
the CMxCON0 register.
Once enabled, the comparator output is latched on the
falling edge of the Timer1 source clock. If a prescaler is
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagram (Figure 15-2) and the Timer1 Block
Diagram (Figure 7-1) for more information.
15.5 Comparator Interrupt
An interrupt can be generated upon a change in the
output value of the comparator for each comparator, a
rising edge detector and a falling edge detector are
present.
When either edge detector is triggered and its
associated enable bit is set (CxINTP and/or CxINTN
bits of the CMxCON1 register), the Corresponding
Interrupt Flag bit (CxIF bit of the PIR2 register) will be
set.
To enable the interrupt, you must set the following bits:
• CxON, CxPOL and CxSP bits of the CMxCON0
register
• CxIE bit of the PIE2 register
• CxINTP bit of the CMxCON1 register (for a rising
edge detection)
• CxINTN bit of the CMxCON1 register (for a falling
edge detection)
• PEIE and GIE bits of the INTCON register
The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
detected while this flag is being cleared, the flag will still
be set at the end of the sequence.
Note:
Although a comparator is disabled, an
interrupt can be generated by changing
the output polarity with the CxPOL bit of
the CMxCON0 register, or by switching
the comparator on or off with the CxON bit
of the CMxCON0 register.
15.6 Comparator Positive Input
Selection
Configuring the CxPCH<1:0> bits of the CMxCON1
register directs an internal voltage reference or an
analog pin to the non-inverting input of the comparator:
• CxIN0+ analog pin
• DAC Reference Voltage (dac_ref)
• FVR Reference Voltage (fvr_ref)
• VSS (Ground)
See Section 13.0 “Fixed Voltage Reference (FVR)”
for more information on the Fixed Voltage Reference
module.
See Section 14.0 “Digital-to-Analog Converter
(DAC) Module” for more information on the DAC input
signal.
Any time the comparator is disabled (CxON = 0), all
comparator inputs are disabled.
15.7 Comparator Negative Input
Selection
The CxNCH0 bit of the CMxCON0 register selects the
analog input pin to the comparator inverting input.
Note:
To use CxIN0+ and CxIN1x- pins as
analog input, the appropriate bits must be
set in the ANSEL register and the
corresponding TRIS bits must also be set
to disable the output drivers.
15.8 Comparator Response Time
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the comparator
differs from the settling time of the voltage reference.
Therefore, both of these times must be considered when
determining the total response time to a comparator
input change. See the Comparator and Voltage Refer-
ence Specifications in Section 22.0 “Electrical Specifi-
cations” for more details.
15.9 Interaction with the COG Module
The comparator outputs can be brought to the COG
module in order to facilitate auto-shutdown. If auto-
restart is also enabled, the comparators can be
configured as a closed loop analog feedback to the
COG, thereby creating an analog controlled PWM.
DS40001709A-page 136
Preliminary
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