PIC16F753 Datasheet, PDF(83/238 Page) Microchip Technology – 14/16-Pin, Flash-Based 8-Bit CMOS Microcontrollers

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PIC16F753 Datasheet, PDF (83/238 Pages) Microchip Technology – 14/16-Pin, Flash-Based 8-Bit CMOS Microcontrollers

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PIC16F753/HV753

10.2 Compare Mode

Compare mode makes use of the 16-bit Timer1

resource. The 16-bit value of the CCPR1H:CCPR1L

register pair is constantly compared against the 16-bit

value of the TMR1H:TMR1L register pair. When a

match occurs, one of the following events can occur:

â¢ Toggle the CCP1 output

â¢ Set the CCP1 output

â¢ Clear the CCP1 output

â¢ Generate a Special Event Trigger

â¢ Generate a Software Interrupt

The action on the pin is based on the value of the

CCP1M<3:0> control bits of the CCP1CON register. At

the same time, the interrupt flag CCP1IF bit is set.

All Compare modes can generate an interrupt.

Figure 10-2 shows a simplified diagram of the

Compare operation.

FIGURE 10-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

CCP1M<3:0>

Mode Select

CCP1

Pin

Set CCP1IF Interrupt Flag

4 (PIR2)

CCPR1H CCPR1L

Q S Output

R Logic

Match

Comparator

TRIS

Output Enable

TMR1H TMR1L

Special Event Trigger

10.2.1 CCP1 PIN CONFIGURATION

The user must configure the CCP1 pin as an output by

clearing the associated TRIS bit.

Note:

Clearing the CCP1CON register will force

the CCP1 compare output latch to the

default low level. This is not the PORT I/O

data latch.

10.2.2 TIMER1 MODE RESOURCE

In Compare mode, Timer1 must be running in either

Timer mode or Synchronized Counter mode. The

compare operation may not work in Asynchronous

Counter mode.

See Section 7.0 âTimer1 Module with Gate Controlâ

for more information on configuring Timer1.

Note:

Clocking Timer1 from the system clock

(FOSC) should not be used in Compare

mode. In order for Compare mode to

recognize the trigger event on the CCP1

pin, TImer1 must be clocked from the

instruction clock (FOSC/4) or from an

external clock source.

10.2.3 SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen

(CCP1M<3:0> = 1010), the CCP1 module does not

assert control of the CCP1 pin (see the CCP1CON

register).

10.2.4 SPECIAL EVENT TRIGGER

When Special Event Trigger mode is chosen

(CCP1M<3:0> = 1011), the CCP1 module does the

following:

â¢ Resets Timer1

â¢ Starts an ADC conversion if ADC is enabled

The CCP1 module does not assert control of the CCP1

pin in this mode.

The Special Event Trigger output of the CCP1 occurs

immediately upon a match between the TMR1H,

TMR1L register pair and the CCPR1H, CCPR1L regis-

ter pair. The TMR1H, TMR1L register pair is not reset

until the next rising edge of the Timer1 clock. The

Special Event Trigger output starts an A/D conversion

(if the A/D module is enabled). This allows the

CCPR1H, CCPR1L register pair to effectively provide a

16-bit programmable period register for Timer1.

TABLE 10-2: SPECIAL EVENT TRIGGER

Device

CCP1

PIC16F753

PIC16HV753

CCP1

Refer to Section 12.0 âAnalog-to-Digital Converter

(ADC) Moduleâ for more information.

Note 1: The Special Event Trigger from the CCP

module does not set interrupt flag bit

TMR1IF of the PIR1 register.

2: Removing the match condition by

changing the contents of the CCPR1H

and CCPR1L register pair, between the

clock edge that generates the Special

Event Trigger and the clock edge that

generates the Timer1 Reset, will

preclude the Reset from occurring.

ï£ 2013 Microchip Technology Inc.

Preliminary

DS40001709A-page 83

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