PIC16F753 Datasheet, PDF (47/238 Pages) Microchip Technology – 14/16-Pin, Flash-Based 8-Bit CMOS Microcontrollers

5.5 Additional Pin Functions
Every PORTA pin on the PIC16F753 has an interrupt-
on-change option and a weak pull-up option. The next
three sections describe these functions.
5.5.1 ANSELA REGISTER
The ANSELA register (Register 5-5) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Note:
The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
5.5.2 WEAK PULL-UPS
Each of the PORTA pins, except RA3, has an
individually configurable internal weak pull-up. Control
bits WPUx enable or disable each pull-up. Refer to
Register 5-6. Each weak pull-up is automatically turned
off when the port pin is configured as an output. The
pull-ups are disabled on a Power-on Reset by the
RAPU bit of the OPTION_REG register. A weak pull-up
is automatically enabled for RA3 when configured as
MCLR and disabled when RA3 is an I/O. There is no
software control of the MCLR pull-up.
PIC16F753/HV753
5.5.3 INTERRUPT-ON-CHANGE
Each PORTA pin is individually configurable as an
interrupt-on-change pin. Control bits IOCA enable or
disable the interrupt function for each pin. Refer to
Register 5-7. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTA Change Interrupt Flag
bit (IOCIF) in the INTCON register (Register 2-3).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the
interrupt by:
a) Any read of PORTA AND Clear flag bit IOCIF.
This will end the mismatch condition;
OR
b) Any write of PORTA AND Clear flag bit IOCIF
will end the mismatch condition;
A mismatch condition will continue to set flag bit IOCIF.
Reading PORTA will end the mismatch condition and
allow flag bit IOCIF to be cleared. The latch holding the
last read value is not affected by a MCLR nor BOR
Reset. After these Resets, the IOCIF flag will continue
to be set if a mismatch is present.
Note:
If a change on the I/O pin should occur
when any PORTA operation is being
executed, then the IOCIF interrupt flag
may not get set.
5.5.4 SLEW RATE CONTROL
Two of the PORTA pins, RA0 and RA2, are equipped
with high current driver circuitry. The SLRCONA register
provides reduced slew rate control to mitigate possible
EMI radiation from these pins.
 2013 Microchip Technology Inc.
Preliminary
DS40001709A-page 47