PIC16F753 Datasheet, PDF (89/238 Pages) Microchip Technology – 14/16-Pin, Flash-Based 8-Bit CMOS Microcontrollers

PIC16F753/HV753
11.0 COMPLEMENTARY OUTPUT
GENERATOR (COG) MODULE
The primary purpose of the Complementary Output
Generator (COG) is to convert a single output PWM
signal into a two output complementary PWM signal.
The COG can also convert two separate input events
into a single or complementary PWM output.
The COG PWM frequency and duty cycle are
determined by a rising event input and a falling event
input. The rising event and falling event may be the
same source. Sources may be synchronous or
asynchronous to the COG_clock.
The rate at which the rising event occurs determines
the PWM frequency. The time from the rising event
input to the falling event input determines the duty
cycle.
A selectable clock input is used to generate the phase
delay, blanking and dead-band times.
A simplified block diagram of the COG is shown in
Figure 11-1.
The COG module has the following features:
• Two modes of operation:
- Synchronous PWM
- Push-pull
• Selectable clock source
• Independently selectable rising event sources
• Independently selectable falling event sources
• Independently selectable edge or level event
sensitivity
• Independent output enables
• Independent output polarity selection
• Phase delay with independent rising and falling
delay times
• Dead-band control with:
- Independent rising and falling event
dead-band times
- Synchronous and asynchronous timing
• Blanking control with independent rising and
falling event blanking times
• Auto-shutdown control with:
- Independently selectable shutdown sources
- Auto-restart enable
- Auto-shutdown pin override control (high,
low, off, and High-Z)
11.1 Fundamental Operation
11.1.1 SYNCHRONOUS PWM MODE
In synchronous PWM mode, the COG generates a two
output complementary PWM waveform from rising and
falling event sources. In the simplest configuration, the
rising and falling event sources have the same signal,
which is a PWM signal with the desired period and duty
cycle. The COG converts this single PWM input into a
dual complementary PWM output. The frequency and
duty cycle of the dual PWM output match those of the
single input PWM signal. The off-to-on transition of
each output can be delayed from the on-to-off transition
of the other output, thereby creating a time immediately
after the PWM transition where neither output is driven.
This is referred to as dead time and is covered in
Section 11.5 “Dead-Band Control”.
A typical operating waveform, with dead band, generated
from a single CCP1 input is shown in Figure 11-4.
11.1.2 PUSH-PULL MODE
In Push-Pull mode, the COG generates a single PWM
output that alternates every PWM period, between the
two COG output pins. The output drive activates with
the rising input event and terminates with the falling
event input. Each rising event starts a new period and
causes the output to switch to the COG pin not used in
the previous period.
A typical push-pull waveform generated from a single
CCP1 input is shown in Figure 11-6.
Push-Pull mode is selected by setting the GxMD bit of
the COGxCON0 register.
11.1.3 ALL MODES
In addition to generating a complementary output from
a single PWM input, the COG can also generate PWM
waveforms from a periodic rising event and a separate
falling event. In this case, the falling event is usually
derived from analog feedback within the external PWM
driver circuit. In this configuration, high-power
switching transients may trigger a false falling event
that needs to be blanked out. The COG can be
configured to blank falling (and rising) event inputs for
a period of time immediately following the rising (and
falling) event drive output. This is referred to as input
blanking and is described in Section 11.6 “Blanking
Control”.
It may be necessary to guard against the possibility of
circuit faults. In this case, the active drive must be
terminated before the Fault condition causes damage.
This is referred to as auto-shutdown and is described in
Section 11.8 “Auto-shutdown Control”.
A feedback falling event arriving too late or not at all can
be terminated with auto-shutdown or by enabling one of
the Hardware Limit Timer (HLT) event inputs. See
Section 9.0 “Hardware Limit Timer (HLT) Module”
for more information about the HLT.
The COG can be configured to operate in phase
delayed conjunction with another PWM. The active
drive cycle is delayed from the rising event by a phase
delay timer. Phase delay is covered in more detail in
Section 11.7 “Phase Delay”. A typical operating
waveform, with phase delay and dead band, generated
from a single CCP1 input, is shown in Figure 11-5.
 2013 Microchip Technology Inc.
Preliminary
DS40001709A-page 89