XPGA Datasheet, PDF (8/89 Pages) Lattice Semiconductor – The ispXPGA architecture

Lattice Semiconductor
Figure 6. ispXPGA Wide Logic Generator
COUT
WIN2
WIN3
4A
S3
SEL0
4B
XIN2
XIN3
S2
SEL1
SEL3
4C
SEL2
4D
YIN2
YIN3
S1
ispXPGA Family Data Sheet
WLGW0
WLGW1
WLGX0
WLGX1
WLGY0
ZIN2
ZIN3
S0
WLGY1
WLGZ0
WLGZ1
Configurable Sequential Element
There are two registers in each CSE for a total of eight registers in each PFU. This high register count assists in
implementing efficient pipelined applications with no utilization penalty. Each register can be configured as a latch
or D type flip-flop with either synchronous or asynchronous set or reset. Figure 2 shows the signals that feed the
register’s D inputs. Feed-through signals in the architecture ensure that registers are efficiently utilized even if the
accompanying LUT is occupied.
Control Logic
The control signals available to the registers in a PFU are Clock, Clock Enable, and Set/Reset. Figure 7 shows the
various options available to generate the clock signal. As can be seen, the clock signal is the output of a 12:1 MUX
with true and compliment versions available from the 12:1 MUX. Each CSE can chose whether it uses the true or
compliment form of the clock. Figure 8 shows the Set/Reset selection for each PFU in the ispXPGA. A common
8