XPGA Datasheet, PDF (37/89 Pages) Lattice Semiconductor – The ispXPGA architecture

Lattice Semiconductor
ispXPGA Family Data Sheet
Deserializer Timing (Continued)
10B/12B DESERIALIZER DELAY TIMING
SYMBOL N
SYMBOL N+1
SYMBOL N+2
SIN
"1" b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 "0" "1" b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 "0" "1" b0 b1 b2 b3 b4
T_TDSIN
RECCLK
RXD _{SYMBOL N-2}
SYMBOL N-1
SYMBOL N
CDRX_SS DESERIALIZER DELAY TIMING
SYMBOL N
SYMBOL N+1
SYMBOL N+2
SIN
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4
T_DSIN
RECCLK
RXD
SYMBOL N-2
SYMBOL N-1
SYMBOL N
RX_SS DESERIALIZER DELAY TIMING
SS_CLKIN
SIN
T_CKISIN
b6 b7
SYMBOL N
SYMBOL N+1
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5
T_DSIN
SYMBOL N+2
b6 b7 b0 b1 b2
RECCLK
RXD
SYMBOL N-2
SYMBOL N-1
SYMBOL N
INTERNAL TIMING FOR sysHSI BLOCK
RECCLK
LOSS, SYDT,
RXD, CDRLOCK
t_{HSIOUTVALIDPRE}
t_{HSIOUTVALIDPOST}
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