XPGA Datasheet, PDF (28/89 Pages) Lattice Semiconductor – The ispXPGA architecture

Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA PFU Timing Parameters (Continued)
Over Recommended Operating Conditions
Parameter
Description
Reset/Set
t_LASSRO
Asynchronous Set/Reset to Output
t_LASSRPW
Asynchronous Set/Reset Pulse Width
t_LASSRR
Asynchronous Set/Reset Recovery
t_{LSSR_S}
Synchronous Set/Reset Setup Time
t_{LSSR_H}
Synchronous Set/Reset Hold Time
1. t_LCTHRUL quoted bit by bit.
-4
Min.
Max.
—
1.17
—
4.50
—
0.55
-0.03
—
0.03
—
ispXPGA PIC Timing Parameters
Parameter
Description
Register/Latch Delays
t_{IO_CO}
Register Clock to Output Delay
t_{IO_S}
Register Setup Time (Data before Clock)
t_{IO_H}
Register Hold Time (Data after Clock)
t_{IOCE_S}
Register Clock Enable Setup Time
t_{IOCE_H}
Register Clock Enable Hold Time
t_{IO_GO}
Latch Gate to Output Delay
t_{IOL_S}
Latch Setup Time
t_{IOL_H}
Latch Hold Time
t_IOLPD
Latch Propagation Delay (Transparent Mode)
t_IOASRO
Asynchronous Set/Reset to Output
t_IOASRPW
Asynchronous Set/Reset Pulse Width
t_IOASRR
Asynchronous Set/Reset Recovery Time
Input/Output Delays
t_IOBUF
t_IOIN
t_IOEN
t_IODIS
t_IOFT
Output Buffer Delay
Input Buffer Delay
Output Enable Delay
Output Disable Delay
Feed-thru Delay
-4
Min.
Max.
—
1.09
0.05
—
0.06
—
-0.03
—
0.13
—
—
0.91
0.05
—
0.06
—
—
0.10
—
1.26
—
4.50
—
0.25
—
1.06
—
0.76
—
0.56
—
-0.10
—
0.20
-3
Min.
Max.
Units
—
—
—
-0.03
0.03
1.35
5.18
0.63
—
—
ns
ns
ns
ns
ns
Timing v.2.0
-3
Min.
Max.
Units
—
1.25
ns
0.06
—
ns
0.07
—
ns
-0.03
—
ns
0.15
—
ns
—
1.05
ns
0.06
—
ns
0.07
—
ns
—
0.12
ns
—
1.45
ns
—
5.18
ns
—
0.29
ns
—
1.22
ns
—
0.87
ns
—
0.64
ns
—
-0.09
ns
—
0.23
ns
Timing v.2.0
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