XPGA Datasheet, PDF (39/89 Pages) Lattice Semiconductor – The ispXPGA architecture

Lattice Semiconductor
ispXPGA Family Data Sheet
ispXP sysCONFIG Port Timing Specifications
Symbol
Timing Parameter
sysCONFIG Write Cycle Timing
t_SUCS
Input setup time of CS to CCLK rise
t_HCS
Hold time of CS to CCLK Rise
t_SUWD
Input setup time of write data to CCLK rise
t_HWD
Hold time of write data to CCLK rise
t_PRGM
Low time to reset device SRAM
t_WINIT
INIT pulse width
t_IODISS
User I/O disable
t_WRDY
Time to write data into SRAM
t_IOENSS
User I/O enable
t_WH
Write clock High pulse width
t_WL
Write clock Low pulse width
f_MAXW
Write f_MAX
sysCONFIG Read Cycle Timing
t_HREAD
t_SUREAD
t_RH
t_RL
f_MAXR
t_CORD
Hold time of READ to CCLK rise
Input setup time of READ High to CCLK rise
READ clock high pulse width
READ clock low pulse width
Read f_MAX
Clock to out for read data
Min.
12
0
12
0
5
4
—
—
—
12
12
—
0
30
12
15
—
—
Boundary Scan Timing
Parameter
t_BTCP
t_BTCPH
t_BTCPL
t_BTS
t_BTH
t_BTRF
t_BTCO
t_BTCODIS
t_BTCOEN
t_BTCRS
t_BTCRH
t_BUTCO
t_BTUODIS
t_BTUPOEN
Description
TCK [BSCAN] Clock Pulse Width
TCK [BSCAN] Clock Pulse Width High
TCK [BSCAN] Clock Pulse Width Low
TCK [BSCAN] Setup Time
TCK [BSCAN] Hold Time
TCK [BSCAN] Rise/Fall Time
TAP Controller Falling Edge of Clock to Valid Output
TAP Controller Falling Edge of Clock to Valid Disable
TAP Controller Falling Edge of Clock to Valid Enable
BSCAN Test Capture Register Setup Time
BSCAN Test Capture Register Hold Time
BSCAN Test Update Register, Falling Edge of Clock to Valid Output
BSCAN Test Update Register, Falling Edge of Clock to Valid Disable
BSCAN Test Update Register, Falling Edge of Clock to Valid Enable
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max. Units
—
ns
—
ns
—
ns
—
ns
50
ns
—
ms
30
ns
4
ms
30
ns
—
ns
—
ns
25
MHz
—
ns
—
ns
—
ns
—
ns
25
MHz
25
ns
Min.
40
20
20
8
10
50
—
—
—
8
25
—
—
—
Max.
—
—
—
—
—
—
18
18
18
—
—
45
20
20
Units
ns
ns
ns
ns
ns
mV/ns
ns
ns
ns
ns
ns
ns
ns
ns
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