XPGA Datasheet, PDF (42/89 Pages) Lattice Semiconductor – The ispXPGA architecture

Lattice Semiconductor
ispXPGA Family Data Sheet
Signal Descriptions¹ (Continued)
Signal Name
Signal Type
Description
HSImA_CDRRST, HSImB_CDRRST
Input
CDR Reset
HSImA_EXLOSS, HSImB_EXLOSS
Input
External loss indicates data on SIN is invalid, forces LOSS to “1”
HSIm_CSLOCK, HSIm_CSLOCK
Internal Signal Indicates when the CSPLL circuit is locked
sysHSI Block (Source Synchronous Mode)⁶
SS_CLKIN0P, SS_CLKIN1P
Input
P-side of differential clock input
SS_CLKIN0N, SS_CLKIN1N
Input
N-side of differential clock input
SS_CLKOUT0P, SS_CLKOUT1P
Output P-side of differential clock output
SS_CLKOUT0N, SS_CLKOUT1N
Output N-side of differential clock output
CAL0, CAL1
Input
Initiates source synchronous calibration sequence
1. x is a variable for the I/O number.
2. y is a variable for the I/O Bank.
3. z is a variable for the PLL number.
4. m is a variable for the sysHSI block number.
5. A and B refer to the sysHSI block channels.
6. 0 and 1 refer to Source Synchronous group 0 and 1
7. n is a variable for the GCLK and Input number
8. See Logic Signal Connections Table for differential pairing.
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