XPGA Datasheet, PDF (10/89 Pages) Lattice Semiconductor – The ispXPGA architecture

Lattice Semiconductor
Figure 10. ispXPGA PIC
GSR
ispXPGA Family Data Sheet
sysIO
9
From routing
2
From sysHSI block
2
To sysHSI block
Only for PICs
associated with
sysHSI blocks
2
From sysHSI block
2
To sysHSI block
9
From routing
PIO0
PIC
PIO1
2
To routing
To routing
To routing
Only for PICs
associated with
sysHSI blocks
2
To routing
sysIO
OE1 OE0
Programmable Input/Output
The PIO is the building block of a PIC. The PIO has a total of 11 inputs and five outputs. Nine of the 11 inputs are
generated from routing. The inputs from routing are the PIO Input (IN), Feed-Thru (FT), Clock (CLK), Input Clock
Enable (ICE), Input Set/Reset (ISR), Output Clock Enable (OCEN), Output Set/Reset (OSR), PIO Output Enable
(OEN), and PIO Input Enable (IEN). The remaining inputs are the sysIO input buffer signal and the Global Set/
Reset signal. Three of the five outputs (OUT0, OUT1, and OE) feed routing. The last two outputs feed the sysIO
buffer directly as the output and output enable of the sysIO output buffer.
PIOs associated with sysHSI blocks contain two additional inputs and outputs to support the sysHSI block. The two
inputs come from the sysHSI block associated with the PIO, and the two outputs feed the sysHSI block. One of the
inputs routes directly through the PIO to routing, while the other is multiplexed with the Feed-Thru, register bypass,
and Q output of the register to form the OUT1 output of the PIO. The outputs to the sysHSI block are the same sig-
nals as the outputs which feed the sysIO buffers (sysIO Output and sysIO Output Enable).
Each PIO has an input register, an output register, and an output enable register as shown in Figure 11. The input
register path of the PIO has a ‘delay’ option, which slows the data-flow. A two-input OR function of the Global Set/
Reset (GSR) and Set/Reset (ISR or OSR) signals creates the set/reset term for the respective registers. Each PIO
has two pairs of set/reset and clock enable signals. One is exclusive to the input register, whereas the other is com-
mon for both the output and output enable registers. The clock (CLK) is common to all registers in a PIO, and the
polarity of the clock is controllable. The input, output, and the output enable registers can be configured as a latch
or D-type flip-flop. Each PIO is capable of generating an output enable signal, which in turn becomes a PIC output.
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