XPGA Datasheet, PDF (32/89 Pages) Lattice Semiconductor – The ispXPGA architecture

Lattice Semiconductor
ispXPGA Family Data Sheet
sysHSI Block Timing
Figure 23 provides a graphical representation of the SERDES receiver input requirements. It provides guidance on
a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N
input skew tolerance.
Figure 23. Receive Data Eye Diagram Template (Differential)
BIT TIME
V_LVDT = 200mV
1.2 V
JT_TH
EO_SIN
JT_TH
JT_TH : Optimum Threshold Crossing Jitter
The data pattern eye opening at the receive end of a link is considered the ultimate measure of received signal
quality. Almost all detrimental characteristics of a transmit signal and the interconnection link design result in eye
closure. This combined with the eye-opening limitations of the line receiver can provide a good indication of a link’s
ability to transfer error-free data.
Signal jitter is of special interest to system designers. It is often the primary limiting characteristic of long digital
links and of systems with high noise level environments. An interesting characteristics of the clock and data recov-
ery (CDR) portion of the ispXPGA SERDES receiver is its ability to filter incoming signal jitter that is below the
clock recovery PLL bandwidth. For signals with high levels of low frequency jitter, the receiver can detect incoming
data error free, with eye openings significantly less than that shown in Figure 23.
sysHSI Block AC Specifications
Operating Frequency Ranges
Symbol
Description
Mode
Test Condition
Min
f_CLK
REFCLK, SS_CLKIN,
SS_CLKOUT
All
40
SS: no CAL
with eo_SIN
400
f_SIN
Serial Input
SS: CAL
10B12B
with eo_SIN
with eo_SIN
400
400
8B10B
with eo_SIN
400
f_SOUT
Serial Out
LVDS
C_L=5 pF, R_L=100 Ohm
400
1. These max. numbers apply to the -4 speed grade only. For the -3 speed grade, the corresponding numbers are:
SS: no CAL 650
SS: CAL 700
10B12B 800
8B10B
800
Max
250
750¹
800¹
850¹
850¹
850
Unit
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
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