XPGA Datasheet, PDF (26/89 Pages) Lattice Semiconductor – The ispXPGA architecture

Lattice Semiconductor
Figure 22. LVPECL Driver with Three Resistor Pack
ispXPGA
LVPECL Buffer
1/4 of Bourns P/N
CAT 16-PC4F12
A
Rs
Rs
ispXPGA Family Data Sheet
Zo
to LVPECL
differential
receiver
Zo
ispXPGA External Switching Characteristics
Over Recommended Operating Conditions
Parameter
Description
Conditions
t_CO
t_S
t_H
t_SINDLY
t_HINDLY
t_COPLL
t_SPLL
Global Clock Input to Output PIO Output Register
Global Clock Input Setup PIO Input Register without input delay
Global Clock Input Hold
PIO Input Register without input delay
Global Clock Input Setup PIO Input Register with input delay
Global Clock Input Hold
PIO Input Register with input delay
Global Clock Input to Output PIO Output Register using PLL without delay
Global Clock Input Setup
PIO Input Register without input delay using
PLL without delay
t_HPLL
Global Clock Input Hold
PIO Input Register without input delay using
PLL without delay
t_SINDLYPLL Global Clock Input Setup
PIO Input Register with input delay using PLL
without delay
t_HINDLYPLL Global Clock Input Hold
PIO Input Register with input delay using PLL
without delay
-4
Min. Max.
— 7.1
-2.7 —
4.6 —
3.8 —
0.0 —
— 3.3
1.1 —
0.8 —
7.6 —
-4.6 —
-3
Min. Max. Units
— 8.2 ns
-2.3 — ns
5.3 — ns
4.4 — ns
0.0 —
— 3.8 ns
1.3 — ns
1.0 — ns
8.8 — ns
-4.0 — ns
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