|
XPGA Datasheet, PDF (1/89 Pages) Lattice Semiconductor – The ispXPGA architecture | |||
|
ispXPGATM Family
March 2003
Preliminary Data Sheet
â Non-volatile, Inï¬nitely Reconï¬gurable
⢠Instant-on - Powers up in microseconds via
on-chip E2CMOS® based memory
⢠No external conï¬guration memory
⢠Excellent design security, no bit stream to intercept
⢠Reconï¬gure SRAM based logic in milliseconds
â High Logic Density for System-level
Integration
⢠139K to 1.25M system gates
⢠160 to 496 I/O
⢠1.8V, 2.5V, and 3.3V VCC operation
⢠Up to 414Kb sysMEM⢠embedded memory
â High Performance Programmable Function
Unit (PFU)
⢠Four LUT-4 per PFU supports wide and narrow
functions
⢠Dual ï¬ip-ï¬ops per LUT-4 for extensive pipelining
⢠Dedicated logic for adders, multipliers, multiplex-
ers, and counters
â Variable-Length Interconnect Routing
Technology
⢠Optimum speed, power, and ï¬exibility for logic
interconnections
â Flexible Memory Resources
⢠Multiple sysMEM Embedded RAM Blocks
â Single port, Dual port, and FIFO operation
⢠64-bit distributed memory in each PFU
â Single port, Double port, FIFO, and Shift
Register operation
Table 1. ispXPGA Family Selection Guide
â Eight sysCLOCK⢠Phase Locked Loops
(PLLs) for Clock Management
⢠True PLL technology
⢠10MHz to 320MHz operation
⢠Clock multiplication and division
⢠Phase adjustment
⢠Shift clocks in 250ps steps
â sysIO⢠for High System Performance
⢠High speed memory support through SSTL and
HSTL
⢠Advanced buses supported through PCI, GTL+,
LVDS, BLVDS, and LVPECL
⢠Standard logic supported through LVTTL,
LVCMOS 3.3, 2.5, and 1.8
⢠Programmable drive strength for series termination
⢠Programmable bus maintenance
â sysHSI⢠Capability for Ultra Fast Serial
Communications
⢠Up to 850Mbps performance
⢠Up to 20 channels per device
⢠Built in Clock Data Recovery (CDR) and
Serialization and De-serialization (SERDES)
â Flexible Programming, Reconï¬guration,
and Testing
⢠IEEE 1532 and 1149.1 compliant
⢠Microprocessor conï¬guration interface
⢠Program E2CMOS while operating from SRAM
ispXPGA 125
ispXPGA 200
ispXPGA 500
ispXPGA 1200
System Gates
139K
210K
476K
1.25M
PFUs
484
676
1764
3844
LUT-4s
1936
2704
7056
15376
Logic FFs
3.8K
5.4K
14.1K
30.7K
sysMEM Memory
92K
111K
184K
414K
Distributed Memory
30K
43K
112K
246K
EBR
20
24
40
90
sysHSI Channels
4
8
12
20
User I/O
160/176
160/208
336
496
Packaging
256 fpBGA
516 fpBGA1
256 fpBGA
516 fpBGA1
516 fpBGA1
900 fpBGA
680 fpSBGA1
900 fpBGA
1. Thermally enhanced package.
Note: LFX1200B/C is preliminary, LFX125/200/500B/C information is advanced.
© 2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speciï¬cations and information herein are subject to change without notice.
www.latticesemi.com
1
xpga_04
|
▷ |