XPGA Datasheet, PDF (40/89 Pages) Lattice Semiconductor – The ispXPGA architecture

Lattice Semiconductor
ispXPGA Family Data Sheet
Switching Test Conditions
Figure 24 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 8.
Figure 24. Output Test Load, LVTTL and LVCMOS Standards
V_CCO
R1
Device
Output
Test
Point
R2
CL*
*C_L includes test fixture and probe capacitance.
Table 8. Text Fixture Required Components
Test Condition
LVCMOS I/O, (L -> H, H -> L)
Default LVCMOS 1.8 I/O (Z -> H)
R₁
R₂
C_L
106 106 35pF
∞
106 35pF
Timing Reference
LVCMOS 3.3 = V_CCO/2
LVCMOS 2.5 = V_CCO/2
LVCMOS 1.8 = V_CCO/2
0.9V
Default LVCMOS 1.8 I/O (Z -> L)
106
∞ 35pF
0.9V
Default LVCMOS 1.8 I/O (H -> Z)
∞
106 5pF
V_OH - 0.3
Default LVCMOS 1.8 I/O (L -> Z)
106
∞
5pF
V_OL + 0.3
Note: Output test conditions for all other interfaces are determined by the respective standards.
VCCO
LVCMOS 3.3 = 3.0V
LVCMOS 2.5 = 2.3V
LVCMOS 1.8 = 1.65V
1.65V
1.65V
1.65V
1.65V
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