XPGA Datasheet, PDF (4/89 Pages) Lattice Semiconductor – The ispXPGA architecture

Lattice Semiconductor
Figure 1. ispXPGA Block Diagram
ispXPGA Family Data Sheet
PFU
PIC
sysMEM Block
sysCLOCK PLL
sysHSI Block
sysIO Buffer
Programmable Function Unit
The Programmable Function Unit (PFU) is the basic building block of the ispXPGA architecture. The PFUs are
arranged in rows and columns in the device with PFU (1,1) referring to (row 1, column 1). Each PFU consists of
four Configurable Logic Elements (CLEs), four Configurable Sequential Elements (CSEs), and a Wide Logic Gen-
erator (WLG). By utilizing these components, the PFU can implement a variety of functions. Table 3 lists some of
the function capabilities of the PFU.
There are 57 inputs to each PFU and nine outputs. The PFU uses 20 inputs for logic, and 37 inputs drive the con-
trol logic from which six control signals are derived for the PFU.
Table 3. Function Capability of ispXPGA PFU
Function
Look-up table
Wide logic functions
Multiplexing
Arithmetic logic
Single-port RAM
Double-port RAM
Shift register
Capability
LUT-4, LUT-5, LUT-6
Up to 20 input logic functions
2:1, 4:1, 8:1
Dedicated carry chain and booth multiplication logic
16X1, 16X2, 16X4, 32X1, 32X2, 64X1
16X1, 16X2, 32X1
8-bit shift registers (up to 32-bit shift capability)
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