XPGA Datasheet, PDF (34/89 Pages) Lattice Semiconductor – The ispXPGA architecture

Lattice Semiconductor
ispXPGA Family Data Sheet
DESERIALIZER Timing¹
Symbol
Description
Mode Conditions Min.
Max. Units
f_DSIN
SIN Frequency Deviation from REFCLK
8B10B/
10B12B
-100
+100
ppm
eo_SIN
SIN Eye Opening Tolerance
All CDR
SS (Note 1)
0.4
—
UIPP
0.65
—
UIPP
ber
Bit Error Rate
All
—
10^-12
Bits
t_SKRX
Skew Margin Between SIN and SS_CLKIN
SS
t_CKISIN
SS_CLKIN to bit0 of SIN
SS
t_{HSIOUTVALIDPRE} RXD, LOSS, CDRLOCK, SYDT Valid Time
Before RECCLK Falling Edge
All
Note 2
Note 2
Note 3
—
0.125 UIPP
2Bt - t_SKRX 2Bt + t_SKRX ns
t_RCP / 2-0.7
—
ns
t_{HSIOUTVALIDPOST} RXD, LOSS, CDRLOCK, SYDT Valid Time
After RECCLK Falling Edge
All
Note 3 t_RCP / 2-0.7
—
ns
t_DSIN
Bit 0 of SIN Delay to RXD Valid at RECCLK
Falling edge
All CDR
SS
Note 2
1.5t_RCP + 1.5t_RCP +
4.5Bt + 2 4.5Bt + 10
ns
1.5t_RCP + 1.5t_RCP +
1.5Bt + 3 1.5Bt + 15
ns
1. ispXPGA only. RX_SS mode only. This limit is increased if EO is increased.
2. SS Normal Receive Mode (no de-skew option).
3. Internal timing for reference only.
Lock-in Timing
CDRX_SS LOCK-IN (DE-SKEW) TIMING
SIN
MIN. 1200 SYNCPAT
CAL
MIN. 1100 LS CYCLE
CDRLOCK
SYDT
t_SUSYNC
t_CDRLOCK
RXD(0:7)
SYNCPAT
TRAINING SEQUENCE
DATA (SERIAL)
t_HDSYNC
DATA (PARALLEL)
SS MODE DATA TRANSFER
CDR_10B12B LOCK-IN TIMING
SIN
1024 SYNCPAT
CDRLOCK
SYDT
t_CDRLOCK
RXD(0:9)
SYNCPAT
DATA (SERIAL)
DATA (PARALLEL)
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