XPGA Datasheet, PDF (19/89 Pages) Lattice Semiconductor – The ispXPGA architecture

Lattice Semiconductor
ispXPGA Family Data Sheet
Table 7. sysHSI Block REFCLK Selections¹
sysHSI Block
Available Global Clock Nets
0
CLK0, CLK1, CLK2, CLK3
1
CLK0, CLK1, CLK2, CLK4
2
CLK0, CLK1, CLK2, CLK5
3
CLK0, CLK1, CLK3, CLK6
4
CLK0, CLK1, CLK3, CLK7
5
CLK0, CLK3, CLK5, CLK7
6
CLK0, CLK2, CLK5, CLK7
7
CLK0, CLK1, CLK5, CLK6
8
CLK0, CLK5, CLK6
9
CLK0, CLK5, CLK6, CLK7
1. Table 6 applies to all devices. Ignore sysHSI blocks not available
in a specific device.
Configuration and Programming
The ispXPGA family of devices takes a unique approach to FPGA configuration memory. It contains two types of
memory, Static RAM and non-volatile E²CMOS cells. The static RAM is used to control the functionality of the
device during normal operation and the E²CMOS memory cells are used to load the SRAM. The E²CMOS memory
module can be thought of as the hard drive for the ispXPGA configuration and the SRAM as the working configura-
tion memory. There is a one-to-one relationship between SRAM memory and the E²CMOS cells. The SRAM can be
configured either from the E²CMOS memory or from an external source, as shown in Figure 21.
Figure 21 shows the different ports and modes that are used in the configuration and programming of the ispXPGA
devices. There are two possible ports that can be used for configuration of the SRAM memory: the ISP port which
is compliant to the IEEE 1149.1 Test Access Port (TAP) Std. and the ISP port which accommodates bit-wide config-
uration. The sysCONFIG port allows byte-wide configuration of the SRAM configuration memory. When program-
ming the E²CMOS memory, only the 1149.1 TAP can be used.
Configuration and programming done through the 1149.1 Test Access Port (TAP) are fully compliant to both the
IEEE Std. 1149.1 Boundary Scan TAP specification and the IEEE Std. 1532 In-System Configuration specification.
To configure or program the device using the 1149.1 TAP the device must be in the ISP mode. To configure the
SRAM memory using the sysCONFIG Port, the device must be in the sysCONFIG mode. Upon power-up, the
device’s SRAM memory can be configured either from the E²CMOS memory or from an external source through
the sysCONFIG mode. Additionally, the SRAM can be re-configured from the E²CMOS memory by executing a
“REFRESH.” See Lattice technical note number TN1026, ispXP Configuration Usage Guide, for more in depth
information on the different programming modes, timing and wake-up, available at www.latticesemi.com.
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