XPGA Datasheet, PDF (33/89 Pages) Lattice Semiconductor – The ispXPGA architecture

Lattice Semiconductor
ispXPGA Family Data Sheet
LOCKIN Time
Symbol
t_SCLOCK
Description
CSPLL Lock Time
t_CDRLOCK
CDRPLL Lock-in Time
t_SYNC
SyncPat Length
t_CAL
CAL Duration
t_SUSYNC
SyncPat Set-up Time to CAL
t_HDSYNC
SyncPat Hold Time from CAL
1. REFCLK clock period.
Mode
All
SS
10B12B
8B10B
SS
SS
SS
SS
Condition
After Input is Stabilized
With SS mode Sync Pattern
With 10B12B Sync Pattern
With 8B10B Idle Pattern
Min.
—
—
—
—
1200
1100
50
50
Max.
25
1024
1024
480
—
—
—
—
Units
µS
t_RCP¹
t_RCP
t_RCP
t_RCP
t_RCP
t_RCP
t_RCP
REFCLK and SS_CLKIN Timing
Symbol
f_DREFCLK
t_JPPREFCLK
t_PWREFCLK
t_RFREFCLK
Description
Frequency Deviation Between TX REFCLK and
CDRX REFCLK on one link.
REFCLK, SS_CLKIN Peak-to-Peak Period Jitter
REFCLK, SS_CLKIN Pulse Width, (80% to 80% or
20% to 20%).
REFCLK, SS_CLKIN Rise/Fall Time. (20% to 80%
or 80% to 20%)
Mode
8B10B,
10B12B
All
All
Condition Min.
-100
40-250 (MHz) -0.005
1
Max.
100
0.005
—
Units
ppm
UIPP
ns
All
—
2
ns
SERIALIZER Timing¹
Symbol
Description
Mode
Condition
Min.
Max.
Units
t_JPPSOUT
SOUT Peak-to-Peak Output Data Jitter
All
—
SOUT Peak-to-Peak Random Jitter
8B10B 900 Mbps w/k28.7-
—
t_JPP8B10B
SOUT Peak-to-Peak Deterministic Jitter 8B10B 900 Mbps w/k28.5+
—
0.25
UIPP
130
ps
110
ps
t_RFSOUT
SOUT Output Data Rise/Fall Time (20%, ^LVDS
80%)
BLVDS
—
700
ps
—
900
ps
t_COSOUT
REFCLK to SOUT Delay
SS/8B10B
10B12B
2Bt² + 2
2Bt² + 10
ns
1Bt² + 2
1Bt² + 10
ns
t_SKTX
Skew of SOUT with Respect to
SS_CLKOUT
SS
—
250
ps
t_CKOSOUT
SS_CLKOUT to bit0 of SOUT
SS
2Bt² + t_SKTX 2Bt² + t_SKTX ns
t_HSITXDDATAS TXD Data Setup Time
All Note 3
1.5
—
ns
t_HSITXDDATAH TXD Data Hold Time
All Note 3
—
1.0
ns
1. The SIN and SOUT jitter specifications listed above are under the condition that the clock tree that drives the REFCLK to sysHSI Block is in
sysCLOCK PLL BYPASS mode.
2. Bt = bit time period. High speed serial bit time.
3. Internal timing for reference only.
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