XPGA Datasheet, PDF (27/89 Pages) Lattice Semiconductor – The ispXPGA architecture

Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA PFU Timing Parameters
Over Recommended Operating Conditions
Parameter
Description
Functional Delays
LUTs
t_LUT4
4-Input LUT Delay
t_LUT5
5-Input LUT Delay
t_LUT6
6-Input LUT Delay
Shift Register (LUT)
t_{LSR_S}
Shift Register Setup Time
t_{LSR_H}
Shift Register Hold Time
t_{LSR_CO}
Shift Register Clock to Output Delay
Arithmetic Functions
t_LCTHRUR
MC (Macro Cell) Carry In to MC Carry Out Delay (Rip-
ple)
t_LCTHRUL¹
t_LSTHRU
t_LSINCOUT
t_LCINSOUTR
t_LCINSOUTL
Feed-thru
MC Carry In to MC Carry Out Delay (Look Ahead)
MC Sum In to MC Sum Out Delay
MC Sum In to MC Carry Out Delay
MC Carry In to MC Sum Out Delay (Ripple)
MC Carry In to MC Sum Out Delay (Look Ahead)
t_LFT
PFU Feed-Thru Delay
Distributed RAM
t_{LRAM_CO}
Clock to RAM Output
t_{LRAMAD_S}
Address Setup Time
t_{LRAMD_S}
Data Setup Time
t_{LRAMWE_S}
Write Enable Setup Time
t_{LRAMAD_H}
Address Hold Time
t_{LRAMD_H}
Data Hold Time
t_{LRAMWE_H}
Write Enable Hold Time
t_LRAMCPW
Clock Pulse Width (High or Low)
t_LRAMADO
Address to Output Delay
Register/Latch Delays
Registers
t_{L_CO}
t_{L_S}
t_{L_H}
t_{LCE_S}
t_{LCE_H}
Latches
Register Clock to Output Delay
Register Setup Time (Data before Clock)
Register Hold Time (Data after Clock)
Register Clock Enable Setup Time
Register Clock Enable Hold Time
t_{L_GO}
t_{LL_S}
t_{LL_H}
t_LLPD
Latch Gate to Output Delay
Latch Setup Time
Latch Hold Time
Latch Propagation Delay (Transparent Mode)
-4
Min.
Max.
—
0.44
—
0.79
—
0.93
-0.62
—
0.63
—
—
0.75
—
0.09
—
0.05
—
0.45
—
0.31
—
0.39
—
0.28
—
0.16
—
1.33
-0.40
—
0.22
—
0.46
—
0.60
—
0.11
—
0.12
—
3.00
—
—
0.93
—
0.62
0.14
—
-0.12
—
-0.11
—
0.11
—
—
0.10
0.14
—
-0.12
—
—
0.10
-3
Min.
Max.
—
0.51
—
0.91
—
1.07
-0.53
—
0.72
—
—
0.86
—
0.10
—
0.06
—
0.52
—
0.36
—
0.45
—
0.32
—
0.18
—
1.53
-0.34
—
0.25
—
0.53
—
0.69
—
0.13
—
0.14
—
3.45
—
—
1.07
—
0.71
0.16
—
-0.10
—
-0.09
—
0.13
—
—
0.12
0.16
—
-0.10
—
—
0.12
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
27