XPGA Datasheet, PDF (38/89 Pages) Lattice Semiconductor – The ispXPGA architecture

Lattice Semiconductor
ispXPGA Family Data Sheet
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Symbol
Parameter
Conditions
Min Max
t_PWH
Input clock, high time
80% to 80%
1.2
—
t_PWL
Input clock, low time
20% to 20%
1.2
—
t_R, t_F
Input Clock, rise and fall time
20% to 80%
—
3.0
t_INSTB
Input clock stability, cycle to cycle (peak)
— +/- 250
f_MDIVIN
M Divider input, frequency range
10
320
f_MDIVOUT
M Divider output, frequency range
10
320
f_NDIVIN
N Divider input, frequency range
10
320
f_NDIVOUT
N Divider output, frequency range
10
320
f_VDIVIN
V Divider input, frequency range
100 400
f_VDIVOUT
V Divider output, frequency range
10
320
t_OUTDUTY
output clock, duty cycle
40
60
t_JIT(CC)
Output clock, cycle to cycle jitter (peak)
Clean reference.
10 MHz < f_MDIVOUT < 20 MHz or
100MHz < f_VDIVIN < 160 MHz
— +/- 250
Clean reference.
20 MHz < f_MDIVOUT < 320 MHz and — +/- 150
160MHz < f_VDIVIN < 320 MHz
T_JIT(PERIOD)
Output clock, period jitter (peak)
Clean reference.
10 MHz < f_MDIVOUT < 20 MHz or
100MHz < f_VDIVIN < 160 MHz
— +/- 300
Clean reference.
20 MHz < f_MDIVOUT < 320 MHz and — +/- 150
160MHz < f_VDIVIN < 320 MHz
t_{CLK_OUT_DELAY} Input clock to CLK_OUT delay
Internal feedback
—
3.0
t_PHASE
Input clock to external feedback delta
External feedback
—
600
t_LOCK
Time to acquire phase lock after input stable
—
25
t_{PLL_DELAY}
Delay increment (Lead/Lag)
Typical = +/- 250ps
+/- 120 +/- 550
t_RANGE
Total output delay range (lead/lag)
+/- 0.84 +/- 3.85
t_{PLL_RSTW}
Minimum reset pulse width
—
1.8
t_{CLK_IN}³
Global clock input delay
—
1.0
t_{PLL_SEC_DELAY} Secondary PLL output delay (t_{PLL_DELAY})
—
1.5
1. This condition assures that the output phase jitter will remain within specification
2. Accumulated jitter measured over 10,000 waveform samples
3. Internal timing for reference only.
Units
ns
ns
ns
ps
MHz
MHz
MHz
MHz
MHz
MHz
%
ps
ps
ps
ps
ns
ps
us
ps
ns
ns
ns
ns
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