XPGA Datasheet, PDF (20/89 Pages) Lattice Semiconductor – The ispXPGA architecture

Lattice Semiconductor
Figure 21. ispXP Block Diagram
Port
ISP 1149.1 TAP Port
ispXPGA Family Data Sheet
sysCONFIG Peripheral Port
ISP BACKGND
1532
Mode
Programming
in seconds
E²CMOS
Memory Space
Memory Space
Power-up
Refresh
Download in
microseconds
sysCONFIG
Configuration
in milliseconds
SRAM
Memory Space
IEEE 1149.1-Compliant Boundary Scan Testability
All ispXPGA devices have boundary scan cells and are compliant with the IEEE 1149.1 standard. This allows func-
tional testing of the circuit board on which the device is mounted through a serial scan path that can access all crit-
ical logic notes. Internal boundary scan registers are linked internally, allowing test data to be shifted in and loaded
directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices
can be linked into a board-level serial scan path for more board level testing.
Security Scheme
A programmable security scheme is provided on the ispXPGA devices as a deterrent to unauthorized copying of
the array configuration patterns. Once programmed, the security scheme prevents read-back of the programmed
pattern by a device programmer, securing proprietary designs from competitors. The entire device must be erased
in order to erase the security scheme.
Density Shifting
The ispXPGA family has been designed to ensure that different density devices in the same package have the
same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from
lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design targeted
for a high-density device to a lower density device. However, the exact details of the final resource utilization will
impact the likely success in each case.
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